Quick Revision Notes — Computer Organization & Architecture

Introduction

These revision notes condense the entire Computer Organization and Architecture syllabus into a quick-read format. Perfect for the night before your exam or a 30-minute refresher before an interview. Each section captures the core concepts, key differences, and critical facts you absolutely must remember.

Unit 1: Introduction and Basic Concepts

Computer Organization vs Architecture

• Architecture: What the programmer sees — instruction set, addressing modes, data types (logical design)
• Organization: How it is implemented — clock speed, control signals, memory technology (physical design)
• Same architecture, different organizations: Intel i3 vs i7 share x86 architecture but differ in organization

Von Neumann Architecture

• Single memory for both instructions and data (von Neumann bottleneck)
• Components: CPU (ALU + CU), Memory, I/O, System Bus
• Instructions fetched and executed sequentially
• Harvard Architecture alternative: Separate instruction and data memories (used in DSPs, ARM caches)

Functional Units

• Input Unit: Accepts data from outside world
• Output Unit: Sends results to outside world
• Memory Unit: Stores instructions and data
• ALU: Performs arithmetic and logical operations
• Control Unit: Coordinates all operations, generates control signals

Unit 2: Data Representation

Number Systems

• Binary (base 2), Octal (base 8), Decimal (base 10), Hexadecimal (base 16)
• Conversion methods: Division-remainder (integer), multiply-and-carry (fractional)

Signed Number Representations

• Sign-magnitude: MSB is sign, remaining bits are magnitude. Two zeros.
• 1's complement: Invert all bits for negative. Two zeros. End-around carry in addition.
• 2's complement: Invert + add 1. One zero. Most used in modern hardware. Range: -2ⁿ⁻¹ to 2ⁿ⁻¹-1

IEEE 754 Floating Point

• Single: 1 + 8 + 23 bits, bias 127
• Double: 1 + 11 + 52 bits, bias 1023
• Special values: Zero (all zeros), Infinity (exponent all 1s, mantissa 0), NaN (exponent all 1s, mantissa non-zero)
• Denormalized numbers: Exponent = 0, implicit leading 0 (not 1)

Error Detection

• Parity: Single bit added — detects odd number of errors
• Hamming code: Multiple check bits — can correct single-bit errors, detect double-bit
• CRC: Polynomial division — powerful detection for burst errors

Unit 3: Register Transfer and Microoperations

Register Transfer Language (RTL)

• Notation: R1 ← R2 means "transfer contents of R2 to R1"
• Conditional: P: R1 ← R2 means "if P=1, transfer R2 to R1"
• Memory reference: R1 ← M[AR] (load), M[AR] ← R1 (store)

Types of Microoperations

• Arithmetic: Add, subtract, increment (R1 ← R1 + 1), decrement, complement
• Logic: AND, OR, XOR, NOT — performed bitwise
• Shift: Logical (zeros fill), Arithmetic (sign preserved), Circular/Rotate (bits wrap around)
• Transfer: Register-to-register, bus transfer

ALU Design

• Combinational circuit: Takes two inputs + operation select → produces result + status flags
• Flags: Carry (C), Zero (Z), Sign/Negative (N), Overflow (V)

Unit 4: CPU Organization

Processor Registers

• PC (Program Counter): Address of next instruction
• IR (Instruction Register): Holds current instruction
• MAR (Memory Address Register): Address to be accessed
• MDR/MBR (Memory Data Register): Data read/written
• ACC (Accumulator): Holds ALU result
• SP (Stack Pointer): Top of stack address
• PSW/FLAGS: Status register with condition flags

Control Unit Types

Stack Organization

• LIFO (Last In, First Out)
• Operations: PUSH (SP ← SP-1, M[SP] ← data) and POP (data ← M[SP], SP ← SP+1)
• Used for: Function calls, expression evaluation, interrupt handling

Unit 5: Instruction Set Architecture

Instruction Format Types

• Three-address: ADD R1, R2, R3 → Most flexible, longer instructions
• Two-address: ADD R1, R2 → Result overwrites first operand
• One-address: ADD X → Uses accumulator (ACC ← ACC + M[X])
• Zero-address: ADD → Uses stack (pop two, operate, push result)

Addressing Modes (Remember the 7 main ones)

1. Immediate: Operand in instruction. Fast, limited range.
2. Direct: Address in instruction. Simple.
3. Indirect: Address points to address of operand. Pointer access.
4. Register: Operand in register. Fastest.
5. Register Indirect: Register holds address. Array traversal.
6. Indexed: Base + offset. Array element access.
7. Relative: PC + offset. Branch targets.

RISC vs CISC

• RISC: Simple instructions, fixed length, many registers, single-cycle, hardware CU, load/store
• CISC: Complex instructions, variable length, fewer registers, multi-cycle, micro CU, memory-to-memory

Unit 6: Memory Organization

Memory Hierarchy (top = fastest, smallest; bottom = slowest, largest)

1. Registers (< 1 ns, bytes)
2. L1 Cache (1-2 ns, 32-64 KB)
3. L2 Cache (3-10 ns, 256 KB - 2 MB)
4. L3 Cache (10-30 ns, 4-64 MB)
5. Main Memory/RAM (50-100 ns, 4-64 GB)
6. SSD (50-200 μs, 256 GB - 4 TB)
7. HDD (5-10 ms, 1-20 TB)

Cache Mapping

• Direct Mapped: Block i maps to line (i mod N). Simple, conflict misses.
• Fully Associative: Block goes anywhere. No conflict misses, expensive comparators.
• Set Associative: N-way = N blocks per set. Balance of both.

Replacement Policies

• LRU (best hit rate, expensive), FIFO (simple), Random (surprisingly good)

Write Policies

• Write-through + No-write-allocate (simple, more traffic)
• Write-back + Write-allocate (complex, less traffic, most used)

Virtual Memory

• Logical address → Physical address translation via page table
• TLB caches recent translations (hit: 1 cycle, miss: page table walk ~100 cycles)
• Page fault: Page not in RAM → fetch from disk (millions of cycles!)

Unit 7: I/O Organization

Three I/O Methods

1. Programmed I/O: CPU polls device status in a loop. Wastes CPU time.
2. Interrupt-Driven: Device signals CPU when ready. CPU free between interrupts.
3. DMA: Dedicated controller handles transfer. CPU only involved at start/end.

DMA Operation

• CPU programs DMA: start address, count, direction
• DMA takes bus control, transfers data block
• Sends interrupt when done
• Cycle stealing: DMA steals one bus cycle at a time from CPU

Interrupt Types

• Hardware interrupt: External device signal
• Software interrupt: INT instruction (system calls)
• Maskable: Can be disabled (most I/O devices)
• Non-maskable: Cannot be disabled (critical errors, power failure)

Unit 8: Pipelining

Basic Pipeline (5-stage RISC)

IF → ID → EX → MEM → WB (Fetch → Decode → Execute → Memory → Writeback)

Hazards

• Structural: Resource conflict → duplicate hardware
• Data (RAW): True dependency → forwarding/bypassing
• Control: Branch uncertainty → prediction, delayed branch

Forwarding Paths

• EX/MEM → EX: Forward ALU result to next instruction's execute stage
• MEM/WB → EX: Forward memory load result to execute (1 stall for load-use)

Branch Handling

• Stall (simple, slow)
• Predict Not Taken (good for loops with few iterations)
• Predict Taken (good for backward branches/loops)
• Dynamic prediction (1-bit, 2-bit saturating counter)

Unit 9: Parallel Processing

Flynn's Classification

• SISD: Uniprocessor
• SIMD: Vector/GPU (same operation on multiple data)
• MISD: Rare (systolic arrays, fault tolerance)
• MIMD: Multiprocessor/multicore (most common parallel architecture)

Key Concepts

• Superscalar: Multiple instructions issued per cycle in single core
• VLIW: Compiler packs multiple operations into one long instruction word
• Multicore: Multiple CPU cores on one chip, each independently executing
• GPU: Thousands of simple cores for massive data parallelism

Exam Tips — Common Mistakes to Avoid

1. Confusing hit rate with miss rate in AMAT calculations
2. Forgetting pipeline register overhead in speedup calculations
3. Mixing up 2's complement overflow rules
4. Not accounting for all three hazard types in pipeline problems
5. Confusing physical vs logical addresses in virtual memory
6. Using wrong bias value in IEEE 754 (127 for single, 1023 for double)