Bus System

Introduction

Imagine a city with all its buildings but no roads — nothing could function because nothing could communicate. In a computer, buses are those roads. A bus is a shared communication pathway consisting of a set of parallel wires (or traces on a circuit board) that transfers data between components. Understanding the bus system is crucial because bus design often determines overall system performance — the fastest CPU in the world is useless if it can't get data fast enough from memory.

What is a Bus?

A bus is a group of electrical conductors (wires or traces) that carry signals between two or more components. Unlike point-to-point connections (which would require a separate wire between every pair of components), a bus is shared — multiple devices connect to the same set of wires and take turns using them.

Bus Characteristics

• Width: Number of parallel lines (e.g., 64-bit data bus = 64 wires for data)
• Clock Speed: How fast signals change (measured in MHz or GHz)
• Bandwidth: Data transfer rate = Width × Clock Speed (e.g., 64 bits × 1 GHz = 8 GB/s)
• Multiplexed vs Dedicated: Some buses share wires for multiple purposes (address and data on same wires alternately)

Types of Buses by Function

Data Bus

• Carries the actual information (data values, instruction codes)
• Bidirectional — data can flow in either direction
• Width equals the word size in simple systems (32 or 64 bits typically)
• Wider = more data per transfer = higher throughput

Address Bus

• Carries the location (address) of data in memory or I/O
• Unidirectional — CPU sends addresses to memory/devices
• Width determines addressable memory: 2ⁿ locations for n-bit address bus
• Example: 32-bit address bus → 2³² = 4,294,967,296 addresses (4 GB)

Control Bus

• Carries command and synchronization signals
• Individual lines have dedicated functions:
• Read/Write: Direction of data transfer
• Memory/IO: Whether accessing memory or I/O device
• Clock: Timing reference
• Interrupt Request: Device requesting attention
• Bus Request/Grant: Arbitration signals
• Reset: System reset signal

Types of Buses by Position

Processor (Internal) Bus

• Connects components within the CPU (ALU, registers, internal cache)
• Very fast (operates at CPU clock speed)
• Very short (on-chip distances)

System Bus (Front-Side Bus)

• Connects CPU to main memory and chipset
• Moderate speed (faster than I/O bus, slower than processor bus)
• Example: Intel's FSB ran at 100-400 MHz (quad-pumped to effective 1600 MHz)

I/O Bus (Expansion Bus)

• Connects peripheral devices
• Slower than system bus (devices don't need CPU-speed access)
• Examples: PCIe, USB, SATA

Memory Bus

• Dedicated connection between memory controller and RAM modules
• Optimized for memory access patterns (burst transfers)
• Example: DDR5 running at 4800-8400 MT/s

Bus Hierarchy in Modern Systems

Modern computers don't use a single bus — they use a hierarchy:

Note: In modern Intel/AMD systems, the Northbridge is integrated into the CPU itself.

Bus Arbitration

Since multiple devices share the bus, there must be rules about who gets to use it. Bus arbitration determines which device (bus master) gets control when multiple devices want the bus simultaneously.

Centralized Arbitration

Daisy Chain (Serial):

• Priority flows through devices in a chain
• Closest device to the arbiter has highest priority
• Simple but unfair — distant devices may starve

Parallel (Independent Request):

• Each device has its own request and grant line to the central arbiter
• Arbiter uses a priority scheme (fixed priority, rotating priority, etc.)
• Fair but requires more wires

Decentralized Arbitration

• No central arbiter — devices collectively decide
• Each device monitors the bus and uses a protocol to resolve conflicts
• Used in some high-performance systems

Synchronous vs Asynchronous Buses

Synchronous Bus

• All transfers synchronized to a common clock signal
• Simple and fast for fixed-speed devices
• Every device must operate at bus clock speed
• Problem: bus speed limited by the slowest device or longest wire

Asynchronous Bus

• No common clock — uses handshaking signals instead:

1. Master asserts "Request" with address and data
2. Slave acknowledges with "Ready"
3. Master releases, slave releases

• Accommodates devices of different speeds
• More complex but more flexible

Bus Performance

Key Metrics

• Bandwidth: Maximum data transfer rate (bytes/second)
• Latency: Time from request to first data delivery
• Throughput: Actual data rate under real workload (usually less than bandwidth)

Bandwidth Calculation

Example: 64-bit bus at 1 GHz with single transfer per cycle:

Improving Bus Performance

• Wider buses: More bits per transfer
• Faster clock: More transfers per second
• Burst mode: Transfer consecutive addresses without re-addressing
• Pipelining: Overlap address phase of next transfer with data phase of current
• Split transactions: Release bus while waiting for slow responses

Modern Bus Standards

Trend: Serial vs Parallel

Ironically, modern "buses" are mostly serial (one bit at a time per lane) rather than parallel. Why? At high speeds, parallel wires suffer from signal skew (bits arriving at different times). Serial links with high clock rates and multiple lanes (like PCIe) achieve higher bandwidth more reliably.

Key Takeaways

1. A bus is a shared communication pathway connecting computer components
2. Three functional types: data bus (carries values), address bus (carries locations), control bus (carries commands)
3. Bus width and clock speed determine bandwidth
4. Bus arbitration resolves conflicts when multiple devices want the bus
5. Modern systems use a bus hierarchy — fast buses near the CPU, slower buses for I/O
6. Synchronous buses use a clock; asynchronous buses use handshaking
7. Modern high-speed "buses" are actually serial links (PCIe, USB) for better signal integrity