Main Memory

Introduction

Main memory (RAM) is where your running programs and their data reside. It's the primary workspace of the computer — large enough to hold multiple active programs but fast enough to keep the CPU fed (with cache assistance). Understanding main memory technology — DRAM, memory modules, interleaving, and DDR — helps explain system performance characteristics and design decisions.

DRAM Technology

How DRAM Works

Each DRAM cell stores one bit using a tiny capacitor and a transistor:

• Capacitor charged = logic 1
• Capacitor discharged = logic 0
• The transistor acts as a gate for reading/writing

The Refresh Problem

Capacitors leak charge over time — after a few milliseconds, the data would be lost. DRAM must be refreshed periodically (every ~64 ms) — each row is read and rewritten to restore charge. This is why it's called Dynamic RAM (as opposed to Static RAM/SRAM which uses flip-flops and doesn't need refresh).

DRAM Access Sequence

1. Row activation (RAS): Select a row — the entire row is loaded into a row buffer
2. Column access (CAS): Select a column within the active row — specific bits are output
3. Precharge: Prepare the bank for the next access

RAS-CAS-Precharge cycle takes ~50-100 ns total for random access. But sequential access within the same row is much faster (only CAS needed — ~10-15 ns).

Memory Organization

Memory Banks

DRAM is organized into banks that can operate semi-independently:

While one bank is in the precharge phase, another can be accessed — this interleaving hides some latency.

DDR (Double Data Rate) Memory

Evolution

MT/s = Mega-Transfers per second (data transferred on both rising AND falling clock edges — hence "double data rate")

DDR Bandwidth Calculation

Memory Interleaving

Concept

Spread consecutive addresses across multiple memory modules so that while one module is busy (precharging), the next module is already being accessed.

Low-Order Interleaving (Most Common)

Lower address bits select the module; upper bits select the location within module:

When reading addresses 0,1,2,3 sequentially, each goes to a different module — maximum bandwidth!

Benefit

Memory Channels

Modern systems use multiple independent memory channels:

• Single channel: One 64-bit path to memory
• Dual channel: Two 64-bit paths (2× bandwidth)
• Quad channel: Four 64-bit paths (4× bandwidth, server/HEDT platforms)

Each channel has its own set of DIMMs, operating independently and in parallel.

Error Correction in Memory

ECC (Error-Correcting Code) Memory

• Adds extra bits (8 bits per 64-bit word) for Hamming-based error correction
• Detects and corrects single-bit errors; detects double-bit errors
• Essential for servers and critical systems
• ~2-3% performance overhead

Key Takeaways

1. DRAM stores bits in capacitors — dense and cheap but needs periodic refresh
2. Access involves row activation (RAS) + column select (CAS) + precharge
3. DDR transfers data on both clock edges, doubling the effective data rate
4. Memory interleaving hides latency by overlapping accesses to different banks/modules
5. Multi-channel configurations multiply bandwidth proportionally
6. DDR5 provides ~51 GB/s bandwidth with 6400 MT/s data rate
7. ECC memory adds error correction capability for mission-critical systems