RISC Architecture

Introduction

RISC (Reduced Instruction Set Computer) emerged in the 1980s as a revolutionary idea: instead of making individual instructions more powerful, make them simpler and execute them faster. The insight was that 80% of program execution used only 20% of available CISC instructions — so why spend transistors on complex instructions that compilers rarely generate? RISC processors achieve high performance through simplicity: fixed-length instructions, load/store architecture, and many registers that enable efficient pipelining. Today, RISC principles dominate mobile computing (ARM), and RISC-V is emerging as the open-source future of processor design.

RISC Design Principles

The Five Key Principles

1. Simple instructions, single cycle: Each instruction completes in one clock cycle (in the pipeline), enabling predictable timing and efficient pipelining.

1. Fixed-length instruction format: All instructions are exactly 32 bits (4 bytes). This eliminates the complex decode logic needed for variable-length instructions — the CPU always knows where the next instruction starts.

1. Load/Store architecture: Only LOAD and STORE instructions access memory. All computation happens between registers. This simplifies the pipeline because only one stage (MEM) needs memory access logic.

1. Large register file: 32 or more general-purpose registers reduce the need for memory accesses. More registers mean more operands available without loading from memory.

1. Hardwired control unit: Simple instructions do not need microcode — pure combinational logic generates control signals, which is faster than microprogrammed approaches.

Architecture Comparison

Three simple instructions versus one complex instruction. But the RISC versions pipeline perfectly — you can start a new instruction every cycle.

The MIPS Architecture (Classic RISC Example)

Register File

Three Instruction Formats (All 32-bit)

This uniform format means the hardware always knows: bits 31-26 are the opcode, bits 25-21 are the first register, etc. Decode is trivial compared to x86's variable-length chaos.

Pipeline-Friendly Design

Why RISC Pipelines Efficiently

RISC enables this because:

• Fixed-length instructions → IF stage always fetches exactly 4 bytes
• Regular format → ID stage always reads the same register fields
• Load/store separation → Only MEM stage accesses data memory
• Simple operations → EX stage completes in one cycle
• No complex instructions → No multi-cycle operations blocking the pipeline

CISC Pipeline Problems (Solved by RISC)

Register Windows (SPARC Innovation)

The SPARC processor introduced register windows for fast function calls:

When calling a function, the hardware rotates the register window — the caller's "out" registers become the callee's "in" registers automatically. No memory access needed for parameter passing! This eliminates stack operations for most function calls.

RISC-V: The Modern Open RISC

RISC-V (2010, UC Berkeley) is a free, open-source ISA gaining massive traction:

• Clean design without legacy baggage
• Modular: base integer ISA (RV32I/RV64I) + optional extensions (M=multiply, A=atomic, F=float, D=double, V=vector)
• No patents or licensing fees
• Used in: education, embedded systems, and increasingly in commercial chips

Why RISC-V Matters

Performance Analysis: RISC vs CISC

The performance equation: Time = IC × CPI × Clock_period

RISC wins because CPI × Clock improvements more than compensate for higher IC. A RISC processor executing 1.3× more instructions at 1.0 CPI and 1.5× faster clock outperforms a CISC processor with fewer instructions at 3.0 CPI.

Real-World RISC Processors

Key Takeaways

1. RISC achieves high performance through simplicity — simple instructions that pipeline efficiently, not powerful individual instructions
2. Load/store architecture isolates memory access to one pipeline stage, avoiding structural hazards
3. Fixed-length instructions make fetch and decode trivial — no variable-length parsing needed
4. Large register files reduce memory traffic — keeping data in registers avoids slow memory accesses
5. Hardwired control is faster than microcode because there is no extra interpretation layer
6. Modern RISC (ARM, RISC-V) dominates mobile and is expanding into servers/desktops, proving that energy efficiency is increasingly more important than raw instruction complexity