Control Unit

Introduction

If the ALU is the muscle of the CPU, the control unit is the brain. It doesn't compute anything itself — instead, it orchestrates everything else. The control unit reads each instruction, figures out what needs to happen, and then generates the precise sequence of electrical signals that make it happen. Every register transfer, every ALU operation, every memory access is triggered by a control signal from the control unit.

Functions of the Control Unit

The control unit is responsible for:

1. Instruction fetching: Initiating memory reads to get the next instruction
2. Instruction decoding: Interpreting the opcode to determine the required operation
3. Sequencing: Determining the order of micro-operations
4. Control signal generation: Producing signals that activate datapath components
5. Handling exceptions: Responding to interrupts and error conditions

Control Signals Generated

The control unit generates signals for:

Register Control

• Register select (which register to read from or write to)
• Register load (enable writing to a register)
• Register output enable (connect register to bus)

ALU Control

• Operation select (ADD, SUB, AND, OR, etc.)
• Carry input (for subtraction or multi-word arithmetic)

Memory Control

• Memory read (MAR → address bus, receive data on data bus)
• Memory write (MAR → address bus, MBR → data bus)

Bus Control

• Bus enables (which component drives each bus)
• Multiplexer selects (routing data through the datapath)

Sequencing

• PC load (for branches — load new address into PC)
• PC increment (advance to next instruction)
• Timing signals (T0, T1, T2... marking each micro-step)

Control Unit Inputs and Outputs

How the Control Unit Works

Step 1: Fetch Phase

The control unit always starts by fetching the next instruction:

• Asserts: PC→MAR, Memory_Read, MBR→IR, PC_increment
• After this, the instruction is in IR and PC points to the next instruction

Step 2: Decode Phase

The control unit examines the opcode field of IR:

• Determines instruction type (arithmetic, branch, load, store, etc.)
• Sets up the sequence of control signals for execution
• If needed, calculates effective address

Step 3: Execute Phase

Depends entirely on the instruction type:

• ADD R1,R2,R3: Assert "R2→BusA, R3→BusB, ALU=ADD, Result→R1, Load_R1"
• LOAD R1,[X]: Assert "X→MAR, Memory_Read, MBR→R1, Load_R1"
• BEQ label: Check Zero flag; if set, assert "label→PC, Load_PC"

Control Unit Design Approaches

Hardwired Control Unit

Control signals generated directly by combinational logic circuits:

• Inputs: opcode bits + timing counter + flags
• Outputs: all control signals
• Fast (minimal propagation delay)
• Inflexible (changing behavior requires redesigning circuits)
• Used in: RISC processors (simpler instruction sets)

Microprogrammed Control Unit

Control signals stored in a special control memory as microinstructions:

• Each machine instruction maps to a sequence of microinstructions
• Microinstructions specify which control signals to assert each cycle
• Flexible (modify behavior by changing the control memory)
• Slightly slower (extra memory read per micro-step)
• Used in: CISC processors (complex instruction sets)

Timing and Sequencing

The control unit uses a timing mechanism (counter or state machine) to track which micro-step is currently executing:

The number of T-states per instruction varies by instruction complexity:

• Simple register ADD: T0-T3 (4 cycles)
• Memory LOAD: T0-T5 (6 cycles)
• Branch: T0-T4 (5 cycles, potentially)

Control Signals Timing Example

For instruction ADD R3, R1, R2 (R3 ← R1 + R2):

Key Takeaways

1. The control unit is the coordinator — it generates all signals that drive the datapath
2. It takes inputs from the IR (what instruction), clock (when), and flags (conditions)
3. It outputs control signals to registers, ALU, memory, and buses
4. Two implementation approaches: hardwired (fast, rigid) and microprogrammed (flexible, slower)
5. Timing counter tracks which micro-step is executing within each instruction
6. Every machine instruction is decomposed into a sequence of timed micro-operations
7. The control unit's design directly determines how many cycles each instruction takes