Register Transfer Language

Introduction

How do computer engineers describe what happens inside a CPU at the hardware level? They can't just say "add two numbers" — they need precise notation that specifies which registers are involved, when data moves, and under what conditions. Register Transfer Language (RTL) is this notation. It's a symbolic language for describing the micro-operations (tiny data transfers and operations) that make up each machine instruction. Think of it as the "assembly language for hardware designers."

What is Register Transfer Language?

RTL describes the flow of data between registers and the operations performed on that data. It uses simple symbolic notation to express hardware operations concisely:

This is NOT a programming language — it describes hardware behavior. Each RTL statement corresponds to actual signal paths and clock edges in the circuit.

Basic RTL Notation

Registers

Registers are denoted by capital letters, often with numbers:

• R0, R1, R2, ... R7 (general-purpose registers)
• PC (Program Counter)
• IR (Instruction Register)
• MAR (Memory Address Register)
• MBR (Memory Buffer Register)
• AC (Accumulator)

Transfer Operation

The arrow (←) denotes data transfer:

Important: The transfer happens at a specific clock edge. R1's value at that moment is copied to R2.

Simultaneous Transfers

Comma separates operations that happen in the same clock cycle:

Conditional Transfer

A control condition (boolean function) before a colon specifies when the transfer occurs:

This means: "On the next clock edge, IF P=1, THEN R2 gets the value of R1."

RTL Symbols and Conventions

Register Transfer Examples

Simple Data Movement

Arithmetic Operations

Conditional Operations

Memory Operations

Describing an Instruction Cycle in RTL

Fetch Cycle

• T0: Put current instruction address on the address bus
• T1: Read memory AND increment PC (simultaneous)
• T2: Place instruction in IR for decoding

Execute Cycle for ADD instruction (ADD R1, R2)

Execute Cycle for LOAD instruction (LOAD R1, [address])

Execute Cycle for STORE instruction (STORE R1, [address])

Execute Cycle for BRANCH instruction (BZ target)

Register Designation

Individual Bits

Bit Ranges

Control Functions and Timing

In hardware, RTL operations happen at clock edges, controlled by timing signals:

Each combination of timing signal and control condition activates specific register transfers.

Connecting RTL to Hardware

Every RTL statement maps to physical hardware:

• R1 ← R2 means: enable R2's output to the bus AND enable R1's input from the bus
• R3 ← R1 + R2 means: route R1 and R2 to ALU inputs, select ADD operation, route ALU output to R3
• Conditional P: means: AND the control signal P with the clock/enable signals

Key Takeaways

1. RTL is a symbolic notation for describing hardware-level data movements and operations
2. The arrow (←) represents data transfer at a clock edge
3. Commas indicate simultaneous operations; colons indicate conditions
4. Every machine instruction can be decomposed into a sequence of RTL micro-operations
5. RTL bridges the gap between architecture (instruction set) and implementation (control signals)
6. Each RTL statement maps directly to multiplexer settings, register enables, and ALU operations
7. Understanding RTL is essential for designing control units (both hardwired and microprogrammed)