Instruction Pipeline

Detailed design of the instruction pipeline including stages, datapath, and control.

Introduction

The instruction pipeline is arguably the single most important performance technique in computer architecture. It allows a processor to work on multiple instructions simultaneously — just like an assembly line in a factory. While one instruction is being executed, the next is being decoded, and another is being fetched from memory. A 5-stage pipeline can potentially have 5 instructions in progress at once, approaching 5× throughput compared to executing one instruction at a time. This page explains how the classic 5-stage RISC pipeline works in detail.

The Assembly Line Analogy

Think of washing clothes. Without pipelining, you would:

Wash load 1 (30 min)
Dry load 1 (30 min)
Fold load 1 (30 min)
Then start load 2...

Total for 4 loads: 4 × 90 = 360 minutes

With pipelining (overlap stages):

Time	30 60 90 120 150 180
Load 1	Wash Dry Fold
Load 2	Wash Dry Fold
Load 3	Wash Dry Fold
Load 4	Wash Dry Fold

Total: 180 minutes (2× faster!)

The 5-Stage RISC Pipeline

IF	→	ID	→	EX	→	MEM	→	WB
Fetch		Decode		Execute		Memory		Write
								Back

Stage 1: Instruction Fetch (IF)

What happens: Read instruction from memory using the PC as address.

Operations

Instruction ← Memory[PC]

PC ← PC + 4 (point to next instruction)

Store in IF/ID register

- The fetched instruction (32 bits)

- PC+4 (for branch calculations later)

Hardware: Instruction cache (or memory), PC register, adder (+4).

Stage 2: Instruction Decode (ID)

What happens: Decode the instruction and read register operands.

Operations

Decode opcode → determine instruction type

Read registers: A ← Reg[rs], B ← Reg[rt]

Sign-extend immediate field (16→32 bits)

Store in ID/EX register

- Read data A and B

- Sign-extended immediate

- Destination register number

- Control signals (ALUOp, MemRead, MemWrite, RegWrite, etc.)

Key insight: Registers are always read (even if not needed) — it is faster to read speculatively than to wait for decode to determine if reading is needed.

Stage 3: Execute (EX)

What happens: ALU performs the operation or calculates addresses.

Example

For R-type (ADD, SUB, etc.): ALU_Result ← A operation B For Load/Store: ALU_Result ← A + sign_extended_immediate (effective address) For Branch: ALU_Result ← A - B (comparison) Branch_target ← PC + (immediate × 4) Store in EX/MEM register: - ALU result - B value (for store) - Destination register - Zero flag (for branch)

Stage 4: Memory Access (MEM)

What happens: Access data memory for loads and stores.

For Load

Mem_Data ← Memory[ALU_Result] (read from computed address)

For Store

Memory[ALU_Result] ← B (write B to computed address)

For other instructions

Pass ALU_Result through (nothing to do with memory)

Store in MEM/WB register

- Memory data (for loads)

- ALU result (for other instructions)

- Destination register

Stage 5: Write Back (WB)

What happens: Write result to the register file.

For Load

Reg[Rd] ← Mem_Data (write loaded data to register)

For R-type

Reg[Rd] ← ALU_Result (write computation result)

For Store/Branch

Nothing written (no register destination)

Pipeline Registers

Pipeline registers store ALL information needed by the next stage:

IF/ID Register

- Instruction [31:0]

- PC+4

ID/EX Register

- ReadData1, ReadData2 (register values)

- Sign-extended immediate

- Rs, Rt, Rd fields

- Control signals: RegDst, ALUSrc, ALUOp, MemRead, MemWrite,

Branch, MemtoReg, RegWrite

EX/MEM Register

- ALU result

- ReadData2 (for store)

- Destination register number

- Zero flag

- Branch target address

- Control: MemRead, MemWrite, Branch, MemtoReg, RegWrite

MEM/WB Register

- Memory data / ALU result

- Destination register

- Control: MemtoReg, RegWrite

Pipeline Timing Example

Execute these 5 instructions:

I1	LW R1, 0(R10)
I2	ADD R2, R3, R4
I3	SUB R5, R6, R7
I4	AND R8, R9, R10
I5	OR R11, R12, R13

Cycle	1 2 3 4 5 6 7 8 9
I1	IF ID EX MEM WB
I2	IF ID EX MEM WB
I3	IF ID EX MEM WB
I4	IF ID EX MEM WB
I5	IF ID EX MEM WB
Total	9 cycles for 5 instructions
Without pipelining	5 × 5 = 25 cycles
Speedup	25/9 = 2.78× (approaches 5× with more instructions)

Pipeline Performance Formulas

Time for n instructions in k-stage pipeline

Total_cycles = k + (n - 1)

Total_time = Total_cycles × Clock_period

Throughput = n / Total_time → approaches 1/Clock_period for large n

Speedup = (n × k × τ) / ((k + n-1) × τ_p) → approaches k for large n

Where

τ = non-pipelined clock period = k × (time per stage)

τ_p = pipelined clock period = max(stage_delay) + register_overhead

Why Pipeline Clock Cycle = Slowest Stage

All stages must complete in one clock cycle. The clock is set by the slowest stage:

Stage delays	IF=200ps, ID=150ps, EX=250ps, MEM=200ps, WB=100ps
Register overhead	20ps
But	Pipeline throughput = 3.7 GHz (one instruction per cycle)

Key Takeaways

The 5-stage pipeline (IF-ID-EX-MEM-WB) allows 5 instructions to be in progress simultaneously
Pipeline registers between stages store all values and control signals needed by the next stage
Pipelining improves throughput (instructions per second) but not latency (time for one instruction)
Clock speed is determined by the slowest pipeline stage — stage balancing is crucial for performance
Ideal speedup equals the number of stages (k) but is never fully achieved due to hazards and overhead
Understanding the pipeline is prerequisite for understanding hazards, forwarding, and all advanced pipeline optimizations

Introduction

The Assembly Line Analogy

Think of washing clothes. Without pipelining, you would:

Wash load 1 (30 min)
Dry load 1 (30 min)
Fold load 1 (30 min)
Then start load 2...

Total for 4 loads: 4 × 90 = 360 minutes

With pipelining (overlap stages):

Time	30 60 90 120 150 180
Load 1	Wash Dry Fold
Load 2	Wash Dry Fold
Load 3	Wash Dry Fold
Load 4	Wash Dry Fold

Total: 180 minutes (2× faster!)

The 5-Stage RISC Pipeline

IF	→	ID	→	EX	→	MEM	→	WB
Fetch		Decode		Execute		Memory		Write
								Back

Stage 1: Instruction Fetch (IF)

What happens: Read instruction from memory using the PC as address.

Operations

Instruction ← Memory[PC]

PC ← PC + 4 (point to next instruction)

Store in IF/ID register

- The fetched instruction (32 bits)

- PC+4 (for branch calculations later)

Hardware: Instruction cache (or memory), PC register, adder (+4).

Stage 2: Instruction Decode (ID)

What happens: Decode the instruction and read register operands.

Operations

Decode opcode → determine instruction type

Read registers: A ← Reg[rs], B ← Reg[rt]

Sign-extend immediate field (16→32 bits)

Store in ID/EX register

- Read data A and B

- Sign-extended immediate

- Destination register number

- Control signals (ALUOp, MemRead, MemWrite, RegWrite, etc.)

Key insight: Registers are always read (even if not needed) — it is faster to read speculatively than to wait for decode to determine if reading is needed.

Stage 3: Execute (EX)

What happens: ALU performs the operation or calculates addresses.

Example

Stage 4: Memory Access (MEM)

What happens: Access data memory for loads and stores.

For Load

Mem_Data ← Memory[ALU_Result] (read from computed address)

For Store

Memory[ALU_Result] ← B (write B to computed address)

For other instructions

Pass ALU_Result through (nothing to do with memory)

Store in MEM/WB register

- Memory data (for loads)

- ALU result (for other instructions)

- Destination register

Stage 5: Write Back (WB)

What happens: Write result to the register file.

For Load

Reg[Rd] ← Mem_Data (write loaded data to register)

For R-type

Reg[Rd] ← ALU_Result (write computation result)

For Store/Branch

Nothing written (no register destination)

Pipeline Registers

Pipeline registers store ALL information needed by the next stage:

IF/ID Register

- Instruction [31:0]

- PC+4

ID/EX Register

- ReadData1, ReadData2 (register values)

- Sign-extended immediate

- Rs, Rt, Rd fields

- Control signals: RegDst, ALUSrc, ALUOp, MemRead, MemWrite,

Branch, MemtoReg, RegWrite

EX/MEM Register

- ALU result

- ReadData2 (for store)

- Destination register number

- Zero flag

- Branch target address

- Control: MemRead, MemWrite, Branch, MemtoReg, RegWrite

MEM/WB Register

- Memory data / ALU result

- Destination register

- Control: MemtoReg, RegWrite

Pipeline Timing Example

Execute these 5 instructions:

I1	LW R1, 0(R10)
I2	ADD R2, R3, R4
I3	SUB R5, R6, R7
I4	AND R8, R9, R10
I5	OR R11, R12, R13

Cycle	1 2 3 4 5 6 7 8 9
I1	IF ID EX MEM WB
I2	IF ID EX MEM WB
I3	IF ID EX MEM WB
I4	IF ID EX MEM WB
I5	IF ID EX MEM WB
Total	9 cycles for 5 instructions
Without pipelining	5 × 5 = 25 cycles
Speedup	25/9 = 2.78× (approaches 5× with more instructions)

Pipeline Performance Formulas

Time for n instructions in k-stage pipeline

Total_cycles = k + (n - 1)

Total_time = Total_cycles × Clock_period

Throughput = n / Total_time → approaches 1/Clock_period for large n

Speedup = (n × k × τ) / ((k + n-1) × τ_p) → approaches k for large n

Where

τ = non-pipelined clock period = k × (time per stage)

τ_p = pipelined clock period = max(stage_delay) + register_overhead

Why Pipeline Clock Cycle = Slowest Stage

All stages must complete in one clock cycle. The clock is set by the slowest stage:

Stage delays	IF=200ps, ID=150ps, EX=250ps, MEM=200ps, WB=100ps
Register overhead	20ps
But	Pipeline throughput = 3.7 GHz (one instruction per cycle)

Key Takeaways

The 5-stage pipeline (IF-ID-EX-MEM-WB) allows 5 instructions to be in progress simultaneously
Pipeline registers between stages store all values and control signals needed by the next stage
Pipelining improves throughput (instructions per second) but not latency (time for one instruction)
Clock speed is determined by the slowest pipeline stage — stage balancing is crucial for performance
Ideal speedup equals the number of stages (k) but is never fully achieved due to hazards and overhead
Understanding the pipeline is prerequisite for understanding hazards, forwarding, and all advanced pipeline optimizations

Introduction

The Assembly Line Analogy

The 5-Stage RISC Pipeline

Stage 1: Instruction Fetch (IF)

Operations

Store in IF/ID register

Stage 2: Instruction Decode (ID)

Operations

Store in ID/EX register

Stage 3: Execute (EX)

Stage 4: Memory Access (MEM)

For Load

For Store

For other instructions

Store in MEM/WB register

Stage 5: Write Back (WB)

For Load

For R-type

For Store/Branch

Pipeline Registers

IF/ID Register

ID/EX Register

EX/MEM Register

MEM/WB Register

Pipeline Timing Example

Pipeline Performance Formulas

Time for n instructions in k-stage pipeline

Where

Why Pipeline Clock Cycle = Slowest Stage

Key Takeaways

Continue learning this concept

Introduction

The Assembly Line Analogy

The 5-Stage RISC Pipeline

Stage 1: Instruction Fetch (IF)

Operations

Store in IF/ID register

Stage 2: Instruction Decode (ID)

Operations

Store in ID/EX register

Stage 3: Execute (EX)

Stage 4: Memory Access (MEM)

For Load

For Store

For other instructions

Store in MEM/WB register

Stage 5: Write Back (WB)

For Load

For R-type

For Store/Branch

Pipeline Registers

IF/ID Register

ID/EX Register

EX/MEM Register

MEM/WB Register

Pipeline Timing Example

Pipeline Performance Formulas

Time for n instructions in k-stage pipeline

Where

Why Pipeline Clock Cycle = Slowest Stage

Key Takeaways

Continue learning this concept