Computer Architecture Projects

Introduction

Building things is the best way to learn computer architecture. When you design a CPU, implement a cache, or simulate a pipeline, abstract concepts become concrete and unforgettable. These projects are designed for B.Tech/BCA students — each one reinforces specific architecture concepts while producing something you can demonstrate in vivas, add to your resume, or use as a starting point for competitive programming and interviews.

Project 1: Single-Cycle MIPS Processor

Difficulty: Intermediate | Duration: 3-4 weeks

Objective

Design and simulate a single-cycle MIPS processor that executes a subset of MIPS instructions.

Supported Instructions

Architecture Block Diagram

Key Design Decisions

1. PC Logic: PC ← PC+4 normally, or branch target, or jump target
2. Instruction Memory: ROM holding the program (separate from data memory — Harvard style)
3. Register File: 32 registers, 2 read ports + 1 write port (all in one cycle)
4. ALU: Performs arithmetic/logic based on ALU control signals
5. Data Memory: RAM for load/store operations
6. Control Unit: Combinational logic generating: RegDst, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite

Implementation in Verilog

Testing

Write a MIPS program in machine code, load it into instruction memory, and verify each instruction produces correct results. Start with simple sequences, then test branches and memory operations.

Project 2: Pipelined Processor with Hazard Detection

Difficulty: Advanced | Duration: 4-6 weeks

Objective

Extend the single-cycle processor to a 5-stage pipeline with forwarding and hazard detection.

New Components

• Pipeline registers: IF/ID, ID/EX, EX/MEM, MEM/WB
• Hazard Detection Unit: Detects load-use hazards, inserts stalls
• Forwarding Unit: Detects RAW hazards, routes data from later stages to earlier stages

Forwarding Unit Logic

Hazard Detection (Load-Use Stall)

Project 3: Cache Simulator

Difficulty: Beginner-Intermediate | Duration: 2 weeks

Objective

Build a configurable cache simulator in Python or C that accepts memory access traces and reports hit/miss statistics.

Features

• Configurable: size, block size, associativity
• Supports: direct-mapped, N-way set-associative, fully associative
• Replacement policies: LRU, FIFO, Random
• Write policies: Write-through, Write-back
• Output: Hit rate, miss rate, miss breakdown (compulsory/capacity/conflict)

Python Implementation Skeleton

Experiments to Run

1. Vary associativity (1, 2, 4, 8-way) — plot hit rate vs associativity
2. Vary block size (8, 16, 32, 64 bytes) — find the sweet spot
3. Compare LRU vs FIFO vs Random on different access patterns
4. Generate traces from matrix multiplication — observe row-major vs column-major differences

Project 4: Branch Predictor Simulator

Difficulty: Intermediate | Duration: 2-3 weeks

Objective

Implement and compare branch prediction strategies.

Predictors to Implement

1. Always Taken / Always Not Taken: Baseline
2. 1-bit predictor: Flip prediction on misprediction
3. 2-bit saturating counter: Requires two consecutive mispredictions to change
4. Two-level adaptive (gshare): Uses global branch history XORed with PC

2-Bit Saturating Counter State Machine

Project 5: Memory Hierarchy Simulator

Difficulty: Intermediate | Duration: 3 weeks

Objective

Simulate the complete memory hierarchy: L1, L2, L3 cache + Main Memory with realistic latencies.

Metrics to Measure

• AMAT at each level
• Bandwidth utilization
• Impact of prefetching
• Cache coherence traffic (for multi-core version)

Project 6: Simple Assembler

Difficulty: Beginner-Intermediate | Duration: 2 weeks

Objective

Write an assembler that converts MIPS assembly text into machine code binary.

Implementation Steps

1. Lexer: Tokenize input (labels, opcodes, registers, immediates)
2. First pass: Build symbol table (label → address mapping)
3. Second pass: Generate machine code using opcode table
4. Output: Binary file or hex dump

This project teaches instruction encoding intimately — you must understand every bit field in every instruction format.

Project Presentation Tips

1. Live demo: Show the simulation running with different inputs
2. Performance graphs: Plot speedup, hit rates, or prediction accuracy
3. Design trade-offs: Explain why you chose specific parameters
4. Comparison: Show how different configurations affect results
5. Real-world connection: Relate your findings to actual processor specifications

Key Takeaways

1. Building a CPU from scratch (even a simple one) teaches you more about architecture than any textbook chapter
2. Cache and branch prediction simulators produce quantitative results you can graph and analyze — great for lab reports
3. The pipeline project with hazard detection shows exactly why modern CPUs are complex
4. These projects build skills directly applicable to hardware verification, embedded systems, and performance engineering careers
5. Start simple (single-cycle), then add complexity (pipeline, hazards, forwarding) — this mirrors how real CPU designs evolved historically