COA Notes
Architecture of embedded processors, microcontrollers, and real-time processing systems.
Introduction
Embedded processors are everywhere — inside your washing machine, car engine controller, smartwatch, elevator, microwave, and traffic lights. Unlike desktop processors optimized for maximum speed, embedded processors are designed for specific tasks with strict constraints on power, cost, size, and real-time response. There are far more embedded processors in the world than desktop CPUs — over 30 billion embedded chips ship annually compared to about 300 million PC processors. Understanding embedded architecture teaches you how to optimize for constraints rather than pure performance.
What Makes Embedded Different
Desktop vs Embedded Design Goals
| Criterion | Desktop CPU | Embedded Processor |
|---|---|---|
| Primary goal | Maximum performance | Meet constraints (power, cost, timing) |
| Power budget | 65-125 W | 10 mW - 5 W |
| Cost target | $100-$500 | $0.50 - $20 |
| Die size | 100-500 mm² | 1-50 mm² |
| Clock speed | 3-5 GHz | 16 MHz - 1 GHz |
| Memory | 16-64 GB external | 32 KB - 2 MB on-chip |
| OS | Full OS (Windows/Linux) | Bare metal or RTOS |
| Real-time? | No (best-effort) | Often yes (hard deadlines) |
Real-Time Requirements
An embedded processor in an airbag controller MUST respond within microseconds — a late response means injury. This is a hard real-time requirement. Architectures supporting this need:
- Deterministic execution time (no cache misses causing unpredictable delays)
- Fast interrupt response (context switch in <1 μs)
- Simple pipeline (predictable timing)
ARM Cortex-M: The Dominant Embedded Architecture
The Cortex-M series powers most modern microcontrollers:
| Cortex-M0/M0+ | Simplest, lowest power, lowest cost |
|---|---|
| 2-stage pipeline, Thumb-2 subset | |
| ~12 μW/MHz, <$0.50 | |
| Cortex-M3 | General purpose embedded |
| 3-stage pipeline, full Thumb-2 | |
| Hardware divide, bit-banding | |
| Cortex-M4 | DSP-capable |
| M3 + single-cycle MAC + optional FPU | |
| Audio processing, motor control | |
| Cortex-M7 | High-performance embedded |
| 6-stage superscalar, branch predict | |
| Dual-issue, caches, 400+ MHz | |
| Cortex-M33 | Security-focused (TrustZone-M) |
| Secure/non-secure worlds |
Cortex-M Architecture Details
Key features for embedded:
- NVIC (Nested Vectored Interrupt Controller): Handles up to 240 interrupts with configurable priorities and 12-cycle worst-case latency
- On-chip Flash: Program memory — no external ROM needed
- On-chip SRAM: Data memory — no external RAM needed
- Peripheral integration: UART, SPI, I2C, ADC, timers all on-chip
Memory Architecture for Embedded
Harvard vs Von Neumann in Embedded
Many embedded processors use true Harvard architecture (separate instruction and data buses):
| CPU | ────► | Unified Flash + SRAM bus |
|---|---|---|
| CPU | ────► | Flash (Program bus) |
| ────► | SRAM (Data bus) |
Tightly-Coupled Memory (TCM)
For hard real-time, caches are problematic (unpredictable hit/miss timing). TCM provides:
- Fixed, deterministic access time (1-2 cycles, always)
- Separate ITCM (instruction) and DTCM (data)
- Programmer explicitly controls what goes in TCM
- Used for time-critical interrupt handlers and data buffers
Power Management Architecture
Low-Power Modes
| Run Mode | CPU active, all peripherals running (~50 mA) |
| Sleep Mode | CPU halted, peripherals active (~5 mA) |
| Deep Sleep | CPU + most peripherals off, RTC running (~10 μA) |
| Standby | Only wakeup logic powered (~1 μA) |
| Shutdown | Almost everything off (~100 nA) |
| Wake-up sources | External interrupt, RTC alarm, watchdog |
| Wake-up time: Sleep | Run: ~1 μs, Deep Sleep→Run: ~5 μs |
Clock Gating
Individual peripherals have clock enables — if you are not using the SPI peripheral, disable its clock, saving dynamic power. This fine-grained control is unique to embedded.
Interrupt Architecture
Embedded systems are fundamentally interrupt-driven:
| │ Priority 0 (Highest) | Hard Fault, NMI │ |
| │ Priority 1 | Safety-critical sensor interrupt │ |
| │ Priority 2 | Motor control timer │ |
| │ Priority 3 | Communication (UART, SPI) │ |
| │ Priority 4 (Lowest) | Background housekeeping │ |
| Tail-chaining | When one ISR completes and another is pending, |
| Late-arriving | Higher-priority interrupt arriving during stacking |
The NVIC provides hardware-managed interrupt nesting — no software overhead for priority management.
Digital Signal Processing (DSP) in Embedded
Many embedded tasks involve signal processing (audio, sensors, motor control). The Cortex-M4/M7 include DSP extensions:
- Single-cycle 32×32 MAC (Multiply-Accumulate): Foundation of FIR filters
- SIMD instructions: Two 16-bit operations simultaneously
- Saturating arithmetic: Prevents overflow wrapping (critical for audio)
- Optional FPU: Single-precision floating point in hardware
Example — FIR filter (common in audio/sensor processing):
Real-World Embedded Applications
Automotive ECU (Engine Control Unit)
- Processor: ARM Cortex-R5 (real-time profile)
- Clock: 400 MHz
- Must calculate fuel injection timing with <10 μs latency
- Reads: 50+ sensors (temperature, pressure, speed, O2)
- Safety: Dual-core lockstep (both cores execute same code, compare results)
Smart Sensor (IoT)
- Processor: Cortex-M0+ at 16 MHz
- Power: 30 μA active, 0.5 μA sleep
- Task: Read temperature every 10 minutes, transmit via BLE
- Battery: Coin cell lasts 5+ years
Motor Controller (Drone)
- Processor: Cortex-M4F at 168 MHz
- Task: Field-Oriented Control (FOC) at 20 kHz loop rate
- Requires: Fast ADC sampling, PWM generation, floating-point math
- Timing: Entire control loop must complete in 50 μs
Key Takeaways
- Embedded processors optimize for constraints (power, cost, real-time) rather than raw speed
- On-chip memory integration eliminates external components, reducing cost and board complexity
- Deterministic timing (TCM, simple pipelines) is critical for real-time applications where caches would add unpredictability
- The NVIC provides hardware interrupt management with sub-microsecond response — essential for event-driven embedded systems
- Power modes allow embedded devices to run for years on batteries by spending most time in ultra-low-power states
- The embedded processor market (by volume) dwarfs the desktop market — understanding these architectures is essential for IoT, automotive, and industrial computing careers
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