ALU Design Project

Step-by-step ALU design project from basic gates to a complete arithmetic logic unit.

Introduction

The Arithmetic Logic Unit is the computational heart of every processor. In this project, you will design a complete 8-bit ALU from scratch — starting with basic logic gates, building up through adders, and finally combining everything into a functional unit that performs addition, subtraction, AND, OR, XOR, NOT, shift, and comparison. By the end, you will understand exactly how the ALU inside your laptop's CPU works at the gate level. This is the same design process hardware engineers at Intel and AMD follow (just at a larger scale with 64-bit words).

Project Overview

Target Specification

│ Inputs	│
│ A[7	0] - First operand (8 bits) │
│ B[7	0] - Second operand (8 bits) │
│ Op[3	0] - Operation select (4 bits) │
│ Outputs	│
│ Result[7	0] - Operation result │

Operation Table

Op[3:0]	Operation	Description
0000	ADD	A + B
0001	SUB	A - B (A + ~B + 1)
0010	AND	A & B (bitwise)
0011	OR	A \	B (bitwise)
0100	XOR	A ^ B (bitwise)
0101	NOT	~A (complement)
0110	SHL	A << 1 (shift left)
0111	SHR	A >> 1 (logical shift right)
1000	SLT	Set if Less Than (signed)
1001	INC	A + 1
1010	DEC	A - 1
1011	PASS	Pass A through unchanged

Phase 1: Building the Full Adder

Everything starts with a 1-bit full adder:

Truth Table

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Boolean Equations

Code example

Sum  = A ⊕ B ⊕ Cin
Cout = (A · B) + (Cin · (A ⊕ B))
     = AB + BCin + ACin  (majority function)

Gate-Level Diagram

A ───┬─────────[XOR]──┬──────[XOR]──── Sum │ │ │ │ B ───┼────┬───────┘ │ Cin──┘ │ │ │ │ │ └──[AND]─────┼────[AND]─┐ │ │ │ │ │ └────[AND]┘ │ │ └──[OR]── Cout │ │ │ │ └────────┼────┘─────────┘ │

Verilog Implementation

Example

module full_adder( input A, B, Cin, output Sum, Cout ); assign Sum = A ^ B ^ Cin; assign Cout = (A & B) | (Cin & (A ^ B)); endmodule

Phase 2: 8-bit Ripple Carry Adder

Chain 8 full adders together:

Example

A7 B7 A6 B6 A5 B5 A1 B1 A0 B0 │ │ │ │ │ │ │ │ │ │ ┌──▼─▼──┐┌──▼─▼──┐┌──▼─▼──┐ ┌──▼─▼──┐┌──▼─▼──┐ C8←─┤FA7 ├┤FA6 ├┤FA5 ├─•─┤FA1 ├┤FA0 ├←─ C0 │ Cin ││ Cin ││ Cin │ │ Cin ││ Cin │ └───┬───┘└───┬───┘└───┬───┘ └───┬───┘└───┬───┘ │ │ │ │ │ S7 S6 S5 S1 S0

The carry ripples from FA0 to FA7. This is simple but slow — worst case, the carry must propagate through all 8 stages.

Delay Analysis

Each full adder: 2 gate delays for carry
8-bit ripple: 2 × 8 = 16 gate delays for carry to reach MSB
Sum at MSB: 16 + 1 = 17 gate delays

For faster addition, we would use a Carry Lookahead Adder (covered in the arithmetic section).

Phase 3: Subtraction Using Adder

Subtraction uses the same adder with 2's complement:

Example

A - B = A + (~B) + 1

We XOR each bit of B with a SUB control signal:

When SUB=0: B passes through unchanged (addition)
When SUB=1: B is inverted, and Cin=1 (subtraction)

Example

SUB signal │ B[i] ───[XOR]──── modified_B[i] → goes into adder │ (When SUB=1, B[i] is inverted) (Set Cin=SUB to add 1 for 2's complement)

Phase 4: Logic Unit

The logic operations are simpler — just bitwise operations on each bit pair:

Example

module logic_unit( input [7:0] A, B, input [1:0] logic_op, // 00=AND, 01=OR, 10=XOR, 11=NOT output reg [7:0] result ); always @(*) begin case(logic_op) 2'b00: result = A & B; 2'b01: result = A | B; 2'b10: result = A ^ B; 2'b11: result = ~A; endcase end endmodule

Phase 5: Shifter

The shift unit moves bits left or right by one position:

Shift Left (SHL)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [B6][B5][B4][B3][B2][B1][B0][ 0 ]

(MSB goes to carry flag, 0 fills LSB)

Logical Shift Right (SHR)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [ 0 ][B7][B6][B5][B4][B3][B2][B1]

(LSB goes to carry flag, 0 fills MSB)

Arithmetic Shift Right (ASR)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [B7][B7][B6][B5][B4][B3][B2][B1]

(Sign bit preserved — fills with MSB)

Phase 6: Complete ALU Integration

Now we combine all units with a multiplexer to select the output:

Adder/		Logic		Shifter
Sub		Unit

Flag Generation

Example

// Zero flag: result is all zeros assign Zero = (Result == 8'b0); // Negative flag: MSB of result assign Negative = Result[7]; // Carry flag: carry out from adder assign Carry = adder_cout; // Overflow: signed overflow detection // Overflow occurs when both inputs have same sign but result has different sign assign Overflow = (A[7] == modified_B[7]) && (Result[7] != A[7]);

Phase 7: Testing and Verification

Test Cases

Test	A	B	Op	Expected Result	Expected Flags
Add positive	0x25	0x1A	ADD	0x3F	Z=0, C=0, V=0, N=0
Add overflow	0x7F	0x01	ADD	0x80	Z=0, C=0, V=1, N=1
Subtract	0x30	0x10	SUB	0x20	Z=0, C=0, V=0, N=0
Sub negative	0x10	0x30	SUB	0xE0	Z=0, C=1, V=0, N=1
AND mask	0xAB	0x0F	AND	0x0B	Z=0, N=0
Zero result	0x55	0x55	XOR	0x00	Z=1, N=0
Shift left	0x81	--	SHL	0x02	C=1

Simulation Waveform

Time	0ns 10ns 20ns 30ns 40ns 50ns
A	0x25 0x7F 0x30 0xAB 0x55 0x81
B	0x1A 0x01 0x10 0x0F 0x55 0x00
Op	ADD ADD SUB AND XOR SHL
Result	0x3F 0x80 0x20 0x0B 0x00 0x02
Zero	0 0 0 0 1 0
Overflow	0 1 0 0 0 0

Design Trade-offs Discussion

Speed vs Area

Ripple carry adder: Small area, slow (O(n) delay)
Carry lookahead: Larger area, fast (O(log n) delay)
Modern ALUs use a hybrid approach

Why These Specific Operations?

The operation set was chosen to match what a real CPU needs:

ADD/SUB: All arithmetic
AND/OR/XOR: Bit manipulation, masking
SHIFT: Multiplication/division by powers of 2
SLT: Comparison for branch conditions (used in MIPS)
INC/DEC: Loop counters, pointer arithmetic

Key Takeaways

The ALU combines an adder, logic unit, and shifter behind a multiplexer — selection controlled by the opcode
Subtraction reuses the adder hardware by inverting B and setting Cin=1 (2's complement trick)
Overflow detection requires checking sign bits — it occurs when the result sign contradicts what the operand signs predict
The Zero flag is simply an 8-input NOR gate on the result bits
This 8-bit ALU scales to 32/64 bits by widening the adder and logic units — the same architecture applies
Real CPU ALUs add more operations (multiply, divide, barrel shift) but follow the same mux-based selection principle

Introduction

Project Overview

Target Specification

│ Inputs	│
│ A[7	0] - First operand (8 bits) │
│ B[7	0] - Second operand (8 bits) │
│ Op[3	0] - Operation select (4 bits) │
│ Outputs	│
│ Result[7	0] - Operation result │

Operation Table

Op[3:0]	Operation	Description
0000	ADD	A + B
0001	SUB	A - B (A + ~B + 1)
0010	AND	A & B (bitwise)
0011	OR	A \	B (bitwise)
0100	XOR	A ^ B (bitwise)
0101	NOT	~A (complement)
0110	SHL	A << 1 (shift left)
0111	SHR	A >> 1 (logical shift right)
1000	SLT	Set if Less Than (signed)
1001	INC	A + 1
1010	DEC	A - 1
1011	PASS	Pass A through unchanged

Phase 1: Building the Full Adder

Everything starts with a 1-bit full adder:

Truth Table

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Boolean Equations

Code example

Sum  = A ⊕ B ⊕ Cin
Cout = (A · B) + (Cin · (A ⊕ B))
     = AB + BCin + ACin  (majority function)

Gate-Level Diagram

Verilog Implementation

Example

module full_adder( input A, B, Cin, output Sum, Cout ); assign Sum = A ^ B ^ Cin; assign Cout = (A & B) | (Cin & (A ^ B)); endmodule

Phase 2: 8-bit Ripple Carry Adder

Chain 8 full adders together:

Example

The carry ripples from FA0 to FA7. This is simple but slow — worst case, the carry must propagate through all 8 stages.

Delay Analysis

Each full adder: 2 gate delays for carry
8-bit ripple: 2 × 8 = 16 gate delays for carry to reach MSB
Sum at MSB: 16 + 1 = 17 gate delays

For faster addition, we would use a Carry Lookahead Adder (covered in the arithmetic section).

Phase 3: Subtraction Using Adder

Subtraction uses the same adder with 2's complement:

Example

A - B = A + (~B) + 1

We XOR each bit of B with a SUB control signal:

When SUB=0: B passes through unchanged (addition)
When SUB=1: B is inverted, and Cin=1 (subtraction)

Example

SUB signal │ B[i] ───[XOR]──── modified_B[i] → goes into adder │ (When SUB=1, B[i] is inverted) (Set Cin=SUB to add 1 for 2's complement)

Phase 4: Logic Unit

The logic operations are simpler — just bitwise operations on each bit pair:

Example

Phase 5: Shifter

The shift unit moves bits left or right by one position:

Shift Left (SHL)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [B6][B5][B4][B3][B2][B1][B0][ 0 ]

(MSB goes to carry flag, 0 fills LSB)

Logical Shift Right (SHR)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [ 0 ][B7][B6][B5][B4][B3][B2][B1]

(LSB goes to carry flag, 0 fills MSB)

Arithmetic Shift Right (ASR)

Input: [B7][B6][B5][B4][B3][B2][B1][B0]

Output: [B7][B7][B6][B5][B4][B3][B2][B1]

(Sign bit preserved — fills with MSB)

Phase 6: Complete ALU Integration

Now we combine all units with a multiplexer to select the output:

Adder/		Logic		Shifter
Sub		Unit

Flag Generation

Example

Phase 7: Testing and Verification

Test Cases

Test	A	B	Op	Expected Result	Expected Flags
Add positive	0x25	0x1A	ADD	0x3F	Z=0, C=0, V=0, N=0
Add overflow	0x7F	0x01	ADD	0x80	Z=0, C=0, V=1, N=1
Subtract	0x30	0x10	SUB	0x20	Z=0, C=0, V=0, N=0
Sub negative	0x10	0x30	SUB	0xE0	Z=0, C=1, V=0, N=1
AND mask	0xAB	0x0F	AND	0x0B	Z=0, N=0
Zero result	0x55	0x55	XOR	0x00	Z=1, N=0
Shift left	0x81	--	SHL	0x02	C=1

Simulation Waveform

Time	0ns 10ns 20ns 30ns 40ns 50ns
A	0x25 0x7F 0x30 0xAB 0x55 0x81
B	0x1A 0x01 0x10 0x0F 0x55 0x00
Op	ADD ADD SUB AND XOR SHL
Result	0x3F 0x80 0x20 0x0B 0x00 0x02
Zero	0 0 0 0 1 0
Overflow	0 1 0 0 0 0

Design Trade-offs Discussion

Speed vs Area

Ripple carry adder: Small area, slow (O(n) delay)
Carry lookahead: Larger area, fast (O(log n) delay)
Modern ALUs use a hybrid approach

Why These Specific Operations?

The operation set was chosen to match what a real CPU needs:

ADD/SUB: All arithmetic
AND/OR/XOR: Bit manipulation, masking
SHIFT: Multiplication/division by powers of 2
SLT: Comparison for branch conditions (used in MIPS)
INC/DEC: Loop counters, pointer arithmetic

Key Takeaways

The ALU combines an adder, logic unit, and shifter behind a multiplexer — selection controlled by the opcode
Subtraction reuses the adder hardware by inverting B and setting Cin=1 (2's complement trick)
Overflow detection requires checking sign bits — it occurs when the result sign contradicts what the operand signs predict
The Zero flag is simply an 8-input NOR gate on the result bits
This 8-bit ALU scales to 32/64 bits by widening the adder and logic units — the same architecture applies
Real CPU ALUs add more operations (multiply, divide, barrel shift) but follow the same mux-based selection principle

Introduction

Project Overview

Target Specification

Operation Table

Phase 1: Building the Full Adder

Truth Table

Boolean Equations

Gate-Level Diagram

Verilog Implementation

Phase 2: 8-bit Ripple Carry Adder

Delay Analysis

Phase 3: Subtraction Using Adder

Phase 4: Logic Unit

Phase 5: Shifter

Shift Left (SHL)

Logical Shift Right (SHR)

Arithmetic Shift Right (ASR)

Phase 6: Complete ALU Integration

Flag Generation

Phase 7: Testing and Verification

Test Cases

Simulation Waveform

Design Trade-offs Discussion

Speed vs Area

Why These Specific Operations?

Key Takeaways

Continue learning this concept

Introduction

Project Overview

Target Specification

Operation Table

Phase 1: Building the Full Adder

Truth Table

Boolean Equations

Gate-Level Diagram

Verilog Implementation

Phase 2: 8-bit Ripple Carry Adder

Delay Analysis

Phase 3: Subtraction Using Adder

Phase 4: Logic Unit

Phase 5: Shifter

Shift Left (SHL)

Logical Shift Right (SHR)

Arithmetic Shift Right (ASR)

Phase 6: Complete ALU Integration

Flag Generation

Phase 7: Testing and Verification

Test Cases

Simulation Waveform

Design Trade-offs Discussion

Speed vs Area

Why These Specific Operations?

Key Takeaways

Continue learning this concept