ALU Design

Introduction

The Arithmetic Logic Unit (ALU) is the computational heart of every processor. It is the circuit that actually performs operations on data — addition, subtraction, AND, OR, XOR, shifts, comparisons, and more. Designing an ALU involves combining several functional units (arithmetic unit, logic unit, shifter) into a single cohesive circuit controlled by operation selection signals from the control unit. Understanding ALU design means understanding how a processor transforms decoded instructions into actual computations.

A well-designed ALU must be fast (it sits on the critical path of instruction execution), area-efficient (it is replicated in superscalar designs), and capable of producing status flags (zero, carry, overflow, negative) that subsequent instructions depend upon.

ALU Block Structure

A typical ALU is organized as three parallel functional blocks feeding a final output multiplexer:

1. Arithmetic Unit: Performs addition, subtraction, increment, decrement, and comparison using an adder circuit with controlled inputs
2. Logic Unit: Performs bitwise AND, OR, XOR, NOT, and other logic operations using parallel gate arrays
3. Shifter: Performs logical shift left, logical shift right, arithmetic shift right, and rotation

The output multiplexer selects which unit's result appears at the ALU output, controlled by operation select lines decoded from the instruction.

Designing the Arithmetic Unit

The arithmetic unit is built around an n-bit adder (typically carry-lookahead for speed). By controlling what enters the adder's two input ports and the carry-in, we can perform multiple arithmetic operations with the same hardware:

The B input is modified by a "B-Logic" block controlled by two select bits (S1, S0): it can pass B unchanged, pass NOT B, pass all zeros, or pass all ones. The carry-in is independently controlled. With these three control signals (S1, S0, Cin), we can select among eight different arithmetic operations.

Designing the Logic Unit

The logic unit performs bitwise operations independently on each bit position. For an n-bit ALU, the logic unit consists of n identical 1-bit slices, each containing the basic gate types with a multiplexer to select the output:

For each bit position i:

• Compute Ai AND Bi
• Compute Ai OR Bi
• Compute Ai XOR Bi
• Compute NOT Ai

A 4-to-1 multiplexer (controlled by two logic-select bits) chooses which operation's result appears at the output. Since there are no carry connections between bit positions, the logic unit has only one gate delay plus the multiplexer delay — it is inherently faster than the arithmetic unit.

Designing the Shifter

The shifter rearranges bits according to the shift type and amount. A barrel shifter can shift by any amount in a single clock cycle using layers of multiplexers. For an n-bit barrel shifter performing shifts of 0 to n-1 positions, the design uses log₂(n) levels of 2-to-1 multiplexers.

For a 32-bit barrel shifter:

• Level 1: Shift by 0 or 16 positions
• Level 2: Shift by 0 or 8 positions
• Level 3: Shift by 0 or 4 positions
• Level 4: Shift by 0 or 2 positions
• Level 5: Shift by 0 or 1 position

Each level's multiplexers are controlled by one bit of the shift amount. The total delay is 5 multiplexer delays regardless of the shift amount — making it a constant-time operation.

Different shift types differ in what fills the vacated positions:

• Logical shift left: fill with 0s
• Logical shift right: fill with 0s
• Arithmetic shift right: fill with the sign bit (preserves sign for signed numbers)
• Rotate: bits that exit one end re-enter the other end

Complete ALU Integration

The complete ALU combines all three units with a top-level multiplexer:

The OpSelect lines (typically 4 bits for 16 operations) encode both which unit to select and which operation within that unit.

The 74181: A Historical Reference Design

The 74181 TTL chip (1970) was a pioneering 4-bit ALU slice that demonstrated practical ALU design. It implemented 16 arithmetic and 16 logic functions selected by 4 function-select inputs (S3-S0) and a mode input (M: M=0 for arithmetic, M=1 for logic). It also output group generate (G) and group propagate (P) signals for carry-lookahead chaining. Four 74181 chips combined with a 74182 carry-lookahead generator created a complete 16-bit ALU.

Condition Flags

The ALU produces condition flags alongside the result, stored in a flags register (also called condition code register or status register):

• Zero (Z): NOR of all result bits — set when result equals zero
• Negative/Sign (N): Copy of the MSB of the result
• Carry (C): Carry-out from the MSB of the adder
• Overflow (V): XOR of carry-in and carry-out of the MSB — indicates signed overflow

These flags are critical for conditional branching (BEQ, BNE, BLT, BGT instructions all test these flags) and for multi-precision arithmetic.

ALU in the CPU Datapath

The ALU connects to the rest of the CPU through internal buses:

1. Input A typically comes from the register file's first read port (source register 1)
2. Input B comes from either the register file's second read port or an immediate value (selected by a MUX)
3. Output goes to the register file's write port and to memory address/data buses
4. Flags go to the condition code register, read by branch decision logic
5. Operation select comes from the control unit based on the decoded instruction opcode

In superscalar processors, multiple ALUs operate in parallel — some specialized for integer arithmetic, others for logic/shift operations, and separate floating-point ALUs for FP operations.

Modern ALU Enhancements

Modern ALUs include features beyond basic operations:

• Leading zero count: Required for floating-point normalization
• Bit manipulation: Bit field extract, insert, reverse operations
• Population count: Counts the number of 1 bits (useful for cryptography and error correction)
• Fused operations: Multiply-accumulate (MAC) for DSP workloads
• SIMD operations: Performing multiple narrow operations in one wide ALU (e.g., four 8-bit adds in a 32-bit ALU)

Key Takeaways

1. The ALU combines arithmetic, logic, and shift units selected by operation control signals
2. The arithmetic unit uses a single adder with controlled inputs to perform add, subtract, increment, decrement, and negate
3. The logic unit performs bitwise operations independently per bit with no carry dependencies
4. A barrel shifter achieves any shift amount in constant time using log₂(n) multiplexer levels
5. Condition flags (Zero, Negative, Carry, Overflow) enable conditional execution and multi-precision arithmetic
6. The ALU sits at the center of the CPU datapath, connecting register file, memory, and control unit
7. Modern superscalar processors include multiple specialized ALUs executing operations in parallel