ARM Architecture

Introduction

ARM (Advanced RISC Machines) is the world's most widely-deployed processor architecture — over 250 billion ARM chips have been manufactured. From the phone in your pocket to the chip controlling your car's brakes, ARM processors are everywhere. What makes ARM special is not raw speed but performance-per-watt — delivering useful computation while sipping minimal power. This page covers the ARM architecture from its RISC foundations through its modern AArch64 incarnation, explaining why it dominates mobile and is increasingly challenging x86 in laptops and servers.

ARM Design Principles

ARM follows RISC philosophy with some unique additions:

1. Load/Store Architecture: Only LDR/STR access memory; all computation between registers
2. Fixed-length instructions: 32-bit in ARM mode, 16/32-bit mixed in Thumb-2
3. Conditional Execution: Every instruction has a 4-bit condition field — execute or skip without branching
4. Barrel Shifter: One operand can be shifted/rotated for free before ALU operation
5. Multiple Load/Store: LDM/STM move multiple registers in one instruction (efficient context switch)
6. Link Register: Function return address stored in register (LR), not on stack

Instruction Set Modes

ARM Mode (32-bit instructions)

All instructions are 32 bits, conditionally executable:

Example — absolute value without branches:

Thumb Mode (16-bit compressed)

Thumb uses 16-bit instructions for common operations:

• Reduces code size by ~30% (important for embedded with limited flash)
• Fewer registers accessible (only R0-R7 in most Thumb-1 instructions)
• Less functionality per instruction

Thumb-2 (Mixed 16/32-bit)

The best of both worlds — compiler chooses 16-bit or 32-bit encoding per instruction:

Modern ARM cores (Cortex-A/M) use Thumb-2 as the primary mode.

AArch64 (64-bit ARM)

ARMv8-A introduced a clean 64-bit architecture:

Register File

Key AArch64 Changes from AArch32

• No conditional execution (except conditional select/compare)
• No multiple load/store (replaced by LDP/STP — load/store pair)
• PC not a general-purpose register (cleaner, safer)
• Simplified addressing modes
• 31 registers instead of 16 (reduces register pressure significantly)

ARM Barrel Shifter

Every data processing instruction can optionally shift one operand:

This means operations like "multiply by 5" are single instructions:

In x86 or MIPS, this would require a separate shift instruction plus an add.

Memory System

Load/Store Instructions

Multiple Register Transfer (AArch32)

NEON SIMD Architecture

ARM's NEON extension provides 128-bit SIMD:

Example — adding 4 floats simultaneously:

Power Efficiency: Why ARM Wins Mobile

ARM's power advantage comes from architectural simplicity:

The 10-15% die area savings from simpler decode translates directly into power savings — those transistors simply do not switch.

ARM Processor Implementations

Key Takeaways

1. ARM's load/store architecture, fixed-length instructions, and conditional execution create a clean, pipeline-friendly design
2. The barrel shifter provides "free" shift operations, reducing instruction count for common patterns
3. Thumb-2 encoding gives ARM competitive code density despite RISC's typically larger programs
4. AArch64 is a clean 64-bit design with 31 registers — reducing spills and improving performance
5. ARM's licensing model enables customization — Apple, Qualcomm, and AWS all create ARM implementations optimized for their specific use cases
6. The simplicity of ARM's decode logic is the primary reason it achieves 3-10× better power efficiency than x86 at equivalent performance levels