Intel 8086 Architecture

Introduction

The Intel 8086, released in 1978, is where the x86 story begins. Every modern Intel and AMD processor — from the Pentium to the latest Core i9 — traces its instruction set lineage directly to this 16-bit chip. Understanding the 8086 is not just history; many of its design decisions (segmented memory, backward compatibility priorities) still influence how computers work today. The 8086 introduced concepts that became standard in computer architecture, and it remains a staple of university COA courses because its complexity is manageable enough to study completely while illustrating real-world design trade-offs.

Architecture Overview

The 8086 is divided into two independent functional units that operate in parallel:

Bus Interface Unit (BIU)

The BIU handles all external bus operations:

• Fetches instructions from memory and places them in the 6-byte prefetch queue
• Generates 20-bit physical addresses from segment:offset pairs
• Handles all memory read/write and I/O operations
• Operates independently — fetches ahead while EU processes current instructions

Execution Unit (EU)

The EU handles instruction execution:

• Reads instructions from the prefetch queue (no direct memory access)
• Decodes instructions and executes them using the ALU
• Manages the general-purpose registers and flags

This BIU/EU split is an early form of pipelining — while the EU executes one instruction, the BIU fetches the next ones.

Register Set

General Purpose Registers (16-bit, split into 8-bit halves)

Pointer and Index Registers (16-bit only)

Segment Registers (16-bit)

Instruction Pointer and Flags

• IP (Instruction Pointer): Offset of next instruction within CS (equivalent to PC in other architectures)
• FLAGS (16-bit):

• CF (Carry), PF (Parity), AF (Auxiliary Carry), ZF (Zero), SF (Sign)
• OF (Overflow), DF (Direction), IF (Interrupt Enable), TF (Trap/Single-step)

Memory Segmentation

The 8086 has a 20-bit address bus (1 MB addressable) but only 16-bit registers. How do you reach 1 MB with 16-bit values? Segmentation.

Physical Address Calculation

Example:

This gives a 20-bit result (00000h to FFFFFh = 1 MB range).

Why Segmentation?

Intel needed to address 1 MB (20-bit addresses) with 16-bit registers. Rather than adding a larger register (which would break the 16-bit design), they used segment registers as a "base" that gets shifted left by 4 bits. This was a pragmatic engineering compromise — it works but creates overlapping segments (many segment:offset pairs point to the same physical address).

Segment Overlap

Multiple logical addresses can map to the same physical address. The maximum segment size is 64 KB (16-bit offset limit).

Instruction Set Categories

The 8086 instruction set has approximately 117 instructions:

Data Transfer

• MOV (register/memory/immediate transfers)
• PUSH/POP (stack operations)
• XCHG (swap two operands)
• IN/OUT (I/O port access)
• LEA (Load Effective Address — calculates address, does not access memory)

Arithmetic

• ADD, ADC (add with carry), SUB, SBB (subtract with borrow)
• MUL/IMUL (unsigned/signed multiply)
• DIV/IDIV (unsigned/signed divide)
• INC, DEC, NEG (negate), CMP

Logic and Shift

• AND, OR, XOR, NOT, TEST
• SHL/SAL, SHR, SAR (arithmetic right shift)
• ROL, ROR, RCL, RCR (rotate through carry)

String Operations

• MOVSB/MOVSW (move string byte/word)
• CMPSB/CMPSW (compare strings)
• SCASB/SCASW (scan string)
• LODSB/STOSB (load/store string)
• REP prefix (repeat CX times)

Control Flow

• JMP (unconditional jump)
• Conditional jumps: JZ, JNZ, JG, JL, JC, JNC, etc.
• LOOP (decrement CX, jump if not zero)
• CALL/RET (subroutine call/return)
• INT/IRET (software interrupt/return)

Bus Cycles and Timing

The 8086 runs at 5-10 MHz. Each bus cycle takes 4 clock cycles (T1-T4):

Minimum/Maximum Mode

• Minimum Mode (MN/MX pin high): 8086 generates its own control signals. Used in simple single-processor systems.
• Maximum Mode (MN/MX pin low): External bus controller (8288) generates control signals. Required for multiprocessor systems with 8087 coprocessor.

Interrupt System

The 8086 supports 256 interrupt types (0-255):

Interrupt Priority (highest to lowest)

1. Division error, INT n, INTO (internal)
2. NMI (non-maskable interrupt)
3. INTR (maskable hardware interrupt)
4. Single-step (TF flag)

Interrupt Sequence

1. Complete current instruction
2. Push FLAGS, CS, IP onto stack
3. Clear IF and TF flags
4. Load CS:IP from interrupt vector table
5. Begin executing ISR (Interrupt Service Routine)

Real-World Legacy

The 8086's design decisions echo through modern computing:

• Backward compatibility: Every x86 processor since 1978 can still run 8086 code
• Segment registers: Evolved into protected-mode selectors in 80286/80386
• Little-endian: Low byte at low address — still used by all x86/x64 processors
• Real mode: Modern CPUs still boot in 8086-compatible real mode before switching to protected/long mode
• I/O port space: Separate from memory space (IN/OUT instructions), still supported

Key Takeaways

1. The 8086's BIU/EU split represents primitive pipelining — fetching and executing overlap
2. Memory segmentation (Segment × 16 + Offset) was a clever hack to get 20-bit addresses from 16-bit registers
3. The register set design (AX/AH/AL split) provided backward compatibility with 8-bit 8080 code
4. 256 interrupt vectors with the IVT at fixed address 0 established the PC interrupt architecture
5. The x86 instruction set, born here, became the world's most commercially successful ISA through relentless backward compatibility
6. Understanding 8086 helps you understand why modern x86 has the quirks it does (variable-length instructions, complex decode, legacy modes)