Instruction Cycle

Introduction

The instruction cycle (also called the machine cycle) is the complete process a CPU goes through to execute a single instruction. While the fetch-decode-execute model gives us the basic idea, real processors have a more nuanced cycle that includes additional phases like operand fetching, indirect addressing resolution, and result storage. Understanding the full instruction cycle reveals exactly how the CPU spends its time and where performance can be improved.

Complete Instruction Cycle Phases

A full instruction cycle consists of up to six sub-cycles:

1. Instruction Fetch (IF): Get the instruction from memory
2. Instruction Decode (ID): Interpret the instruction
3. Operand Address Calculation (AC): Calculate where operands are
4. Operand Fetch (OF): Get the operands from memory/registers
5. Execution (EX): Perform the operation
6. Result Store (WB): Write the result to destination

Not every instruction uses all phases. A register-to-register ADD skips phases 3-4, while a NOP (no operation) might only need phases 1-2.

The Instruction Cycle State Diagram

Phase-by-Phase Details

Instruction Fetch (IF)

The Memory Address Register (MAR) holds the address being accessed. The Memory Buffer Register (MBR) holds the data being read/written.

Instruction Decode (ID)

The control unit examines the opcode portion of the instruction in IR:

• Determines the instruction type (arithmetic, branch, load, store)
• Identifies addressing mode
• Routes control signals to appropriate units
• In microprogrammed control: looks up the microinstruction sequence

Operand Address Calculation (AC)

If the instruction references memory, the effective address must be calculated:

• Immediate: Operand is in the instruction itself — no calculation needed
• Direct: Address field IS the effective address
• Indirect: Address field points to a location containing the real address
• Indexed: Effective address = base + index register + offset
• Register: Operand is in a register — no memory access needed

The Indirect Cycle

When using indirect addressing, an extra memory access is needed:

This cycle can repeat (multiple levels of indirection), adding latency.

Operand Fetch (OF)

Retrieve the actual data values:

Execution (EX)

The ALU performs the specified operation:

• Arithmetic: ADD, SUB, MUL, DIV
• Logic: AND, OR, XOR, NOT
• Shift: Left shift, right shift, rotate
• Branch: Compare and possibly update PC
• I/O: Transfer data to/from device

Result Store (Write Back - WB)

Store the result to the specified destination:

• To a register: Fast, single cycle
• To memory: Requires address bus + data bus + write signal

Timing: How Long Does Each Phase Take?

The huge variation in IF and OF times is due to the memory hierarchy — a cache hit takes 1-3 cycles, but a main memory access takes 100+ cycles.

Instruction Cycle for Different Instruction Types

Data Transfer (MOV, LOAD, STORE)

Move data from one location to another.

Arithmetic/Logic (ADD, AND, SUB)

Compute a result from one or two operands.

Branch (JMP, BEQ, CALL)

Potentially change the sequence of execution.

I/O (IN, OUT)

Communicate with peripheral devices.

Interrupts in the Instruction Cycle

After each instruction completes, the CPU checks for pending interrupts:

Types of interrupts:

• Hardware interrupt: External device needs attention (keyboard, timer, disk)
• Software interrupt: Program requests OS service (system call)
• Exception: Error condition (divide by zero, page fault, illegal instruction)

Performance Metrics

CPI (Cycles Per Instruction)

Average number of clock cycles per instruction:

Typical values: 1-4 for RISC, 3-15 for CISC

CPU Execution Time

MIPS (Million Instructions Per Second)

Key Takeaways

1. The instruction cycle has six possible phases: IF, ID, AC, OF, EX, WB
2. Not all phases are needed for every instruction type
3. Indirect addressing adds extra memory accesses (indirect cycle)
4. Memory access phases (IF, OF, WB) are the primary performance bottleneck
5. Interrupts are checked between instructions and can redirect execution
6. CPI and clock rate together determine execution speed
7. Understanding the instruction cycle is essential for pipeline design (each phase becomes a pipeline stage)