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USB architecture, Thunderbolt, PCIe, and modern peripheral connection standards.
Introduction
Remember when computers had separate ports for keyboard (PS/2 purple), mouse (PS/2 green), printer (parallel port), modem (serial port), and joystick (game port)? USB replaced all of them with a single universal connector. Today, USB-C can carry power, data, video, and audio through one cable. Understanding how USB and other modern interfaces work at the protocol level reveals elegant solutions to complex problems: hot-plugging, automatic device detection, power delivery, and bandwidth sharing among dozens of devices.
USB Architecture Overview
USB System Topology
USB uses a tiered star topology with the host controller at the root:
┌────────────────────────────────────────────────────┐
│ USB System Topology │
│ │
│ ┌──────────────┐ │
│ │ Host Controller │ ← Root (in computer) │
│ └───────┬────────┘ │
│ │ │
│ ┌───────▼────────┐ │
│ │ Root Hub │ │
│ └─┬─────┬─────┬──┘ │
│ │ │ │ │
│ ┌──▼──┐ ┌▼──┐ ┌▼─────────┐ │
│ │Mouse│ │KB │ │ Hub │ │
│ └─────┘ └───┘ └─┬──────┬─┘ │
│ │ │ │
│ ┌─────▼┐ ┌───▼────┐ │
│ │Phone │ │Printer │ │
│ └──────┘ └────────┘ │
└────────────────────────────────────────────────────┘
Key architectural decisions:
- Host-controlled: All communication initiated by the host (computer) — devices never talk without being asked
- Up to 127 devices: 7-bit address space (address 0 reserved for unconfigured devices)
- Up to 7 tiers of hubs (practical limit ~5)
- Polling-based: Host polls devices on a schedule — no bus contention
USB Speed Grades
| Standard | Speed | Year | Typical Use |
|---|---|---|---|
| USB 1.0 (Low Speed) | 1.5 Mbps | 1996 | Keyboard, mouse |
| USB 1.1 (Full Speed) | 12 Mbps | 1998 | Audio devices |
| USB 2.0 (High Speed) | 480 Mbps | 2000 | Flash drives, webcams |
| USB 3.0 (SuperSpeed) | 5 Gbps | 2008 | External drives |
| USB 3.1 Gen 2 | 10 Gbps | 2013 | Fast storage |
| USB 3.2 Gen 2x2 | 20 Gbps | 2017 | NVMe enclosures |
| USB4 | 40/80 Gbps | 2019/2022 | Everything (based on Thunderbolt) |
USB Data Transfer Types
USB supports four transfer types optimized for different needs:
| Transfer Type | Guaranteed Bandwidth | Error Correction | Use Case |
|---|---|---|---|
| Control | No | Yes (retry) | Device setup, configuration |
| Bulk | No (best effort) | Yes (retry) | File transfer, printing |
| Interrupt | Yes (polled regularly) | Yes (retry) | Keyboard, mouse, gamepad |
| Isochronous | Yes (reserved) | No (no retry) | Audio, video streaming |
Why no retries for isochronous? If an audio sample is late, replaying it is worse than skipping it. Real-time data values timeliness over completeness.
USB Protocol Details
Packet Structure
Every USB transaction has three phases:
| Token Packet | Data Packet → Handshake Packet |
| Token | [SYNC][PID][ADDR][ENDP][CRC5] |
| Data | [SYNC][PID][DATA (0-1024 bytes)][CRC16] |
| Handshake | [SYNC][PID] |
Enumeration (Device Discovery)
When you plug in a USB device, this sequence occurs:
- Hub detects voltage change on port (device connection)
- Hub notifies host controller via interrupt transfer
- Host resets the port (signals the device to initialize)
- Device responds at default address 0
- Host reads Device Descriptor (vendor ID, product ID, class)
- Host assigns unique address (1-127)
- Host reads Configuration Descriptor (endpoints, power needs)
- Host selects configuration and loads appropriate driver
- Device is ready to use
This entire process takes 100-500ms — the brief pause you notice when plugging in a USB device.
Power Delivery
USB can deliver power as well as data:
| Standard | Voltage | Current | Power |
|---|---|---|---|
| USB 2.0 | 5V | 500 mA | 2.5W |
| USB 3.0 | 5V | 900 mA | 4.5W |
| USB-PD (Power Delivery) | 5-48V | up to 5A | up to 240W |
USB-PD negotiation:
- Devices communicate power capabilities over CC (Configuration Channel) pins
- Source advertises available voltage/current profiles
- Sink requests desired profile
- Source adjusts output — phone charging, laptop charging, even monitors
PCIe (Peripheral Component Interconnect Express)
Architecture
PCIe replaced the shared parallel PCI bus with point-to-point serial links:
Old PCI (shared bus)
[CPU] ═══ [GPU] ═══ [NIC] ═══ [Sound] (all share bandwidth)
Modern PCIe (point-to-point)
┌─── [GPU] (×16 lanes = 64 GB/s)
[CPU] ───┼─── [NVMe SSD] (×4 lanes = 16 GB/s)
├─── [NIC] (×4 lanes = 16 GB/s)
└─── [WiFi] (×1 lane = 4 GB/s)
Lane and Link Widths
Each PCIe lane is a pair of differential signal pairs (one TX, one RX):
| Generation | Per Lane (each direction) | ×1 | ×4 | ×16 |
|---|---|---|---|---|
| PCIe 3.0 | 1 GB/s | 1 GB/s | 4 GB/s | 16 GB/s |
| PCIe 4.0 | 2 GB/s | 2 GB/s | 8 GB/s | 32 GB/s |
| PCIe 5.0 | 4 GB/s | 4 GB/s | 16 GB/s | 64 GB/s |
| PCIe 6.0 | 8 GB/s | 8 GB/s | 32 GB/s | 128 GB/s |
GPUs use ×16 links because they need massive bandwidth for texture data and rendered frames.
PCIe Protocol Layers
┌───────────────────┐
│ Transaction Layer │ ← Packets (read/write requests and completions)
├───────────────────┤
│ Data Link Layer │ ← Error detection (CRC), flow control, retry
├───────────────────┤
│ Physical Layer │ ← Electrical signaling, encoding (128b/130b)
└───────────────────┘
Thunderbolt
Thunderbolt (developed by Intel and Apple) tunnels multiple protocols through one cable:
Thunderbolt 4/USB4 Cable carries:
├── PCIe data (for storage, eGPU)
├── DisplayPort video (for monitors)
├── USB 3.x data (for peripherals)
└── Power delivery (up to 100W)
All through one USB-C connector!
Thunderbolt 4 provides:
- 40 Gbps total bandwidth
- Dual 4K displays or single 8K
- PCIe tunneling (for external GPU enclosures)
- Daisy-chaining up to 6 devices
SATA vs NVMe
Legacy: SATA
- Designed for spinning hard drives
- Point-to-point serial connection
- Maximum: 600 MB/s (SATA III)
- Queue depth: 32 commands
- Protocol overhead optimized for rotational media
Modern: NVMe (over PCIe)
- Designed from scratch for flash storage
- Direct PCIe connection (no controller bottleneck)
- Maximum: 7+ GB/s (PCIe 4.0 ×4) or 14+ GB/s (PCIe 5.0 ×4)
- Queue depth: 65,535 commands across 65,535 queues
- Parallelism matches flash's internal parallelism
Example
SATA SSD: [NAND Flash] → [SSD Controller] → [SATA Interface] → [SATA Controller] → CPU
↑ Bottleneck! (600 MB/s max)
NVMe SSD: [NAND Flash] → [SSD Controller] → [PCIe Interface] → CPU
↑ Direct path! (7+ GB/s)
Comparing Modern Interfaces
| Interface | Max Speed | Topology | Hot-plug | Power | Primary Use |
|---|---|---|---|---|---|
| USB 3.2 | 20 Gbps | Star/Hub | Yes | 100W | Universal peripheral |
| USB4/TB4 | 40-80 Gbps | Tunnel | Yes | 100-240W | Universal + display |
| PCIe 5.0 ×4 | 16 GB/s | Point-to-point | Limited | N/A | Internal storage/cards |
| SATA III | 600 MB/s | Point-to-point | Yes (eSATA) | N/A | Legacy storage |
| DisplayPort 2.1 | 80 Gbps | Point-to-point/Daisy | Yes | USB-PD | Displays |
| HDMI 2.1 | 48 Gbps | Point-to-point | Yes | No | Displays, TV |
Key Takeaways
- USB's host-controlled, polled architecture enables hot-plugging and automatic configuration — the host discovers and configures devices without user intervention
- Different transfer types (control, bulk, interrupt, isochronous) optimize for different real-time and reliability requirements
- PCIe replaced shared buses with point-to-point serial links, enabling independent full-speed connections to each device
- NVMe over PCIe removes the SATA bottleneck, allowing SSDs to operate at their true speed (10-12× faster than SATA)
- Thunderbolt/USB4 tunnels multiple protocols through one cable — a convergence of power, data, and display into a single universal connector
- Understanding these protocols helps you make informed decisions about system design and understand why certain peripherals perform differently on different ports
Exam Focus
Revise definitions, diagrams, examples, and short-answer points for USB and Modern Interfaces.
Interview Use
Prepare one clear explanation, one practical example, and one common mistake for this Computer Organization & Architecture topic.
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