Superscalar Architecture

Introduction

A superscalar processor can issue and execute multiple instructions in a single clock cycle. While a basic pipelined processor completes at most one instruction per cycle (CPI = 1), a superscalar processor achieves CPI < 1 (or equivalently, IPC > 1). Your laptop's CPU is superscalar — it can execute 4-6 instructions every single clock cycle when conditions are favorable. This page explains how superscalar processors extract instruction-level parallelism from sequential programs.

From Scalar to Superscalar

Issue Width

Modern superscalar processors:

• Intel Golden Cove: 6-wide (6 micro-ops per cycle)
• AMD Zen 4: 6-wide
• Apple M3 Firestorm: 8-wide
• ARM Cortex-X4: 10-wide decode, 6-wide rename

Requirements for Superscalar Execution

1. Multiple Fetch

Fetch multiple instructions per cycle from instruction cache (typically 32 bytes = 8 MIPS instructions or 2-8 x86 instructions).

2. Multiple Decode

Decode all fetched instructions in parallel. For RISC (fixed-length), this is straightforward. For x86 (variable-length), this requires complex logic to find instruction boundaries.

3. Dependency Checking

Before issuing multiple instructions together, hardware must verify no dependencies between them:

4. Multiple Execution Units

Need parallel hardware to actually execute multiple instructions:

5. Multiple Write-Back

The register file needs multiple write ports to accept results from multiple execution units simultaneously.

Static vs Dynamic Superscalar

Static (In-Order Issue)

Hardware issues instructions in program order, limited by dependencies:

In-order superscalar may issue I1+I3 but not I1+I2. Simple but misses opportunities.

Dynamic (Out-of-Order Issue)

Hardware reorders instructions to find independent ones:

Dynamic scheduling (Tomasulo's algorithm, reservation stations) enables this reordering.

Instruction-Level Parallelism (ILP)

ILP is the amount of parallelism available in a program:

Average ILP determines how much a superscalar processor can extract.

Typical ILP Available

Limits to Superscalar Performance

True Data Dependencies

Cannot execute instruction until its inputs are ready. Limits parallelism.

Control Dependencies

Branches create uncertainty — cannot issue past a branch until it resolves (mitigated by prediction).

Resource Conflicts

Only so many ALUs, load units, etc. Two instructions needing the same unit cannot execute simultaneously.

Window Size

Larger instruction window → more opportunity to find parallel instructions → but more complex hardware.

Diminishing Returns

Going from 1-wide to 2-wide: ~40% speedup Going from 2-wide to 4-wide: ~25% speedup Going from 4-wide to 8-wide: ~10% speedup (Amdahl's Law at the instruction level — sequential dependencies limit gains)

Real-World Superscalar Performance

Modern CPUs achieve IPC of 4-6 on favorable code:

Key Takeaways

1. Superscalar processors issue multiple instructions per cycle, achieving CPI < 1 (IPC > 1)
2. Requirements: multiple fetch, decode, dependency checking, execution units, and register file ports
3. Dynamic (out-of-order) scheduling finds more parallelism than static (in-order) by reordering instructions
4. Available ILP is program-dependent — scientific code has more parallelism than branch-heavy integer code
5. Diminishing returns limit practical issue width to 4-8 — wider machines find less additional parallelism
6. Modern desktop CPUs achieve IPC of 4-6, meaning they effectively complete 4-6 instructions every nanosecond-scale clock cycle