Binary Addition

Introduction

Binary addition is the most fundamental arithmetic operation performed by digital computers. Every calculation your processor performs — whether it is running a game, compiling code, or rendering a webpage — ultimately relies on circuits that add binary numbers together. Understanding how addition works at the hardware level gives you insight into why processors are designed the way they are, and why speed improvements in adder circuits have been such a critical area of computer engineering.

At its core, binary addition follows the same rules you learned in elementary school for decimal addition, except there are only two digits: 0 and 1. The addition rules are: 0+0=0, 0+1=1, 1+0=1, and 1+1=10 (which is 0 with a carry of 1). When we add 1+1+1, the result is 11 (which is 1 with a carry of 1). These simple rules are implemented in hardware using logic gates, and from these tiny building blocks, we construct circuits capable of adding 64-bit numbers in a fraction of a nanosecond.

The Half Adder

The half adder is the simplest addition circuit. It takes two single-bit inputs, A and B, and produces two outputs: a Sum bit and a Carry bit. The term "half" comes from the fact that it cannot handle a carry input from a previous stage — it only adds two bits in isolation.

The truth table for a half adder is:

From this truth table, we can derive the Boolean expressions: Sum = A XOR B and Carry = A AND B. The XOR gate produces a 1 when the inputs differ (exactly one input is 1), while the AND gate produces a 1 only when both inputs are 1 — precisely when we need to carry. A half adder requires just two gates: one XOR and one AND.

The Full Adder

The full adder extends the half adder by accepting a third input: the carry-in (Cin) from a previous addition stage. This makes it possible to chain multiple adders together for multi-bit addition. A full adder has three inputs (A, B, Cin) and two outputs (Sum, Cout).

The truth table for a full adder is:

The Boolean expressions are: Sum = A XOR B XOR Cin and Cout = AB + BCin + ACin. The carry-out expression means "a carry is generated when at least two of the three inputs are 1." A full adder can be built from two half adders and an OR gate: the first half adder computes A XOR B and A AND B, the second takes (A XOR B) and Cin, and the final OR combines the two carry signals.

Worked Example: Adding Two 4-Bit Numbers

Let us add 1011 (decimal 11) and 0110 (decimal 6):

Working from right to left: Position 0: 1+0+0=1, carry=0. Position 1: 1+1+0=10, sum=0, carry=1. Position 2: 0+1+1=10, sum=0, carry=1. Position 3: 1+0+1=10, sum=0, carry=1. The final carry gives us 10001, which is decimal 17. This matches 11+6=17.

The Ripple Carry Adder

A ripple carry adder (RCA) connects n full adders in series to add two n-bit numbers. The carry-out of each full adder feeds into the carry-in of the next full adder. For instance, a 4-bit ripple carry adder uses four full adders where the carry-out of bit 0 becomes the carry-in of bit 1, and so on.

The circuit is straightforward to design and uses minimal hardware — just n full adders for an n-bit addition. However, it has a significant drawback: the carry must "ripple" through every stage sequentially. Bit position k cannot produce its final sum until it receives the carry from position k-1. In the worst case (adding 1111...1 + 0000...1), the carry propagates through every single stage.

Delay Analysis

Each full adder introduces a gate delay for carry computation. If each full adder's carry path has a delay of 2 gate delays (one AND level and one OR level in the carry expression), then an n-bit ripple carry adder has a worst-case delay of 2n gate delays. For a 32-bit adder, that is 64 gate delays. At a gate delay of roughly 50 picoseconds in modern technology, this gives about 3.2 nanoseconds — which means a maximum clock frequency of around 300 MHz for just the adder alone. Modern processors running at 4-5 GHz clearly cannot use a simple ripple carry adder on their critical path.

Improving Performance

The performance problem with ripple carry adders motivated the development of faster adder architectures. The carry-lookahead adder (CLA) computes all carries simultaneously using generate and propagate signals, reducing delay to O(log n). The carry-select adder computes sums for both possible carry inputs (0 and 1) in parallel, then selects the correct result when the actual carry arrives. The carry-skip adder identifies groups where the carry would propagate straight through and bypasses them. Each of these designs trades additional hardware for reduced delay.

Practical Circuit Considerations

In real hardware design, the choice of adder depends on the target application. Ripple carry adders are still used in low-power, area-constrained designs like simple embedded microcontrollers where clock speeds are modest. High-performance processors use hybrid designs — perhaps carry-lookahead within 4-bit groups combined with carry-select between groups. FPGA implementations often use dedicated carry chains built into the fabric that provide fast ripple-carry performance without the normal gate-delay penalty.

Key Takeaways

1. Binary addition uses only four rules: 0+0=0, 0+1=1, 1+0=1, 1+1=10
2. The half adder adds two bits using XOR (sum) and AND (carry) gates
3. The full adder adds three bits (including carry-in) and enables multi-bit addition
4. Ripple carry adders chain full adders but suffer O(n) delay due to sequential carry propagation
5. The worst-case delay of a 32-bit ripple carry adder is approximately 64 gate delays
6. Faster adder designs (carry-lookahead, carry-select) trade hardware complexity for reduced latency
7. The choice of adder architecture depends on speed requirements, power budget, and area constraints