Glossary of Terms — Computer Organization & Architecture

Introduction

Computer Organization has hundreds of technical terms, acronyms, and concepts. This glossary provides clear, concise definitions organized alphabetically, with cross-references to related terms. Use this as a quick lookup when you encounter unfamiliar terminology in lectures, textbooks, or exam questions. Each definition aims to give you not just the textbook definition but also the intuitive understanding of why the concept matters.

A

Accumulator: A special register that stores the result of ALU operations. In one-address instruction formats, it is the implicit source and destination (e.g., ADD X means ACC ← ACC + M[X]). Many early processors (8080, 6502) were accumulator-based.

Address Bus: Unidirectional bus carrying the memory address from CPU to memory/I/O. Width determines addressable memory (e.g., 32-bit address bus → 4 GB addressable).

Addressing Mode: The method used to specify the location of an operand in an instruction. Common modes: immediate, direct, indirect, register, indexed, relative. Different modes offer trade-offs between flexibility and instruction size.

ALU (Arithmetic Logic Unit): Combinational circuit that performs arithmetic (add, subtract, multiply) and logical (AND, OR, XOR, NOT) operations. Takes two inputs plus operation select, produces result plus status flags (zero, carry, overflow, sign).

AMAT (Average Memory Access Time): Performance metric for memory hierarchy. Formula: AMAT = Hit_time + Miss_rate × Miss_penalty. Lower AMAT = faster effective memory.

Amdahl's Law: Performance law stating Speedup = 1/[(1-f) + f/S], where f = improvable fraction, S = speedup of that fraction. Shows diminishing returns of partial optimization.

Associative Memory (CAM): Memory that searches by content rather than address. Used in TLBs and fully-associative caches. Every entry compared in parallel — fast but expensive.

B

Barrel Shifter: Hardware unit that can shift/rotate by any number of positions in a single cycle. Used in ARM processors to provide "free" shift operations on one ALU operand.

BIU (Bus Interface Unit): In the 8086, the unit responsible for external bus operations — instruction fetching, memory read/write, and address generation.

Branch Prediction: Technique to guess branch outcome before it is known, allowing the pipeline to continue fetching without stalling. Types: static (always predict taken/not-taken), dynamic (history-based: 1-bit, 2-bit, gshare, TAGE).

Bus: Shared communication pathway connecting computer components. Consists of data bus (carries data), address bus (carries addresses), and control bus (carries signals like Read, Write, Interrupt).

Byte Ordering: How multi-byte values are stored. Big-endian: MSB at lowest address (Motorola, network). Little-endian: LSB at lowest address (Intel x86). ARM supports both (bi-endian).

C

Cache Memory: Small, fast SRAM memory between CPU and main memory that stores recently accessed data. Exploits temporal and spatial locality to reduce average memory access time by 10-100×.

Cache Coherence: In multiprocessor systems, the protocol ensuring all cores see consistent data. Protocols: MESI, MOESI. Problem: one core writes, others have stale copies.

CPI (Cycles Per Instruction): Average clock cycles per instruction for a program. CPI = CPU_time × Clock_rate / Instruction_count. Lower CPI = better performance.

CISC (Complex Instruction Set Computer): Architecture with many complex, variable-length instructions that can perform multi-step operations. Examples: x86, VAX. Trade-off: powerful instructions but harder to pipeline.

Control Unit: CPU component that generates control signals to coordinate all operations. Decodes instructions and sequences microoperations. Types: hardwired (combinational logic) and microprogrammed (ROM-based).

D

Data Bus: Bidirectional bus carrying actual data between CPU, memory, and I/O. Width determines how much data moves per transfer (32-bit, 64-bit).

Data Hazard: Pipeline condition where an instruction depends on the result of a previous instruction still in the pipeline. Types: RAW (true), WAR (anti), WAW (output). Solved with forwarding, stalling, or register renaming.

DMA (Direct Memory Access): I/O technique where a dedicated controller transfers data between memory and device without CPU involvement. CPU only programs the transfer and handles completion interrupt.

DRAM (Dynamic RAM): Main memory technology using capacitors. Dense and cheap but requires periodic refresh (every 64ms). Types: DDR4, DDR5, LPDDR5.

E

Effective Address: The actual memory address computed by the CPU after applying the addressing mode. For indexed mode: effective address = base + index.

Endianness: See Byte Ordering.

Exception: Internal event requiring CPU intervention (divide by zero, page fault, invalid opcode). Unlike interrupts, exceptions are synchronous — triggered by the instruction itself.

F

Flag Register (PSW/Status Register): Register holding condition code bits set by ALU operations. Common flags: Zero (Z), Carry (C), Sign/Negative (N), Overflow (V). Used by conditional branch instructions.

Flynn's Classification: Taxonomy of computer architectures by instruction and data streams. SISD (uniprocessor), SIMD (vector/GPU), MISD (rare), MIMD (multiprocessor/multicore).

Forwarding (Bypassing): Pipeline technique where results from later stages are sent directly to earlier stages (via multiplexers) instead of waiting for writeback. Eliminates most RAW hazard stalls.

G-H

GPU (Graphics Processing Unit): Massively parallel processor with thousands of simple cores optimized for data-parallel workloads (graphics, AI, scientific computing).

Harvard Architecture: Architecture with separate memory/buses for instructions and data. Eliminates structural hazard between fetch and memory access. Used in most L1 cache designs.

Hardwired Control Unit: Control unit implemented with fixed combinational logic (gates, decoders, sequencers). Faster than microprogrammed but difficult to modify. Used in RISC processors.

Hit Rate: Fraction of memory accesses found in cache. Hit_rate = Hits / Total_accesses. Typical L1 hit rates: 90-98%.

I

IEEE 754: Standard for floating-point arithmetic defining formats (single 32-bit, double 64-bit), special values (±0, ±∞, NaN), and rounding modes.

Instruction Pipeline: Technique of overlapping instruction execution by dividing it into stages. Classic 5-stage: IF, ID, EX, MEM, WB.

Interrupt: External asynchronous signal requesting CPU attention. Types: maskable (can be disabled), non-maskable (NMI, cannot be disabled). CPU saves state, jumps to ISR, returns when done.

IPC (Instructions Per Clock): Inverse of CPI. Modern superscalar processors achieve IPC > 1 (multiple instructions completed per cycle).

L-M

Locality of Reference: Principle that programs access a small portion of address space at any time. Temporal locality: recently accessed data likely accessed again. Spatial locality: nearby addresses likely accessed soon.

MAR (Memory Address Register): Register holding the address of the memory location being accessed. Connected to address bus.

MDR (Memory Data Register / MBR): Register holding data being read from or written to memory. Connected to data bus.

Microprogrammed Control Unit: Control unit using a control memory (ROM) storing microinstructions. Each machine instruction maps to a sequence of microinstructions. Flexible and easy to modify but slower than hardwired.

MIPS (Million Instructions Per Second): Performance metric. MIPS = Clock_rate / (CPI × 10⁶). Caution: misleading for comparing different ISAs.

Miss Penalty: Time (in cycles) to fetch a block from the next level on a cache miss. L1 miss penalty to L2: ~10 cycles. L2 to main memory: ~100-200 cycles.

O-P

Out-of-Order Execution: CPU technique where instructions execute in data-ready order rather than program order. Uses register renaming, reservation stations, and ROB to maintain correctness while improving throughput.

Page Table: Data structure mapping virtual page numbers to physical frame numbers. Stored in main memory, cached in TLB for fast lookup.

Pipeline Register: Storage element between pipeline stages holding intermediate results and control signals. Adds latency but enables overlapped execution.

Program Counter (PC): Register holding the address of the next instruction to be fetched. Incremented after each fetch (sequential) or loaded with target address (branch/jump).

R-S

Register File: Array of registers (8-32 architectural, 100+ physical in modern CPUs). Provides fastest storage directly accessible by ALU. Two read ports + one write port typical.

RISC (Reduced Instruction Set Computer): Architecture with simple, fixed-length instructions designed for efficient pipelining. Features: load/store architecture, many registers, single-cycle execution. Examples: ARM, MIPS, RISC-V.

ROB (Reorder Buffer): Hardware structure in out-of-order processors that maintains program order for instruction retirement. Ensures precise exceptions despite out-of-order execution.

SRAM (Static RAM): Fast memory using flip-flops (6 transistors/bit). No refresh needed. Used for cache and registers. More expensive and less dense than DRAM.

Superscalar: Processor that issues multiple instructions per clock cycle using multiple parallel execution units. Achieves IPC > 1 through hardware parallelism extraction.

T-V

TLB (Translation Lookahead Buffer): Cache for virtual-to-physical address translations. Typically fully associative, 32-1024 entries. TLB miss: expensive page table walk required.

Two's Complement: Most common signed integer representation. Range: -2ⁿ⁻¹ to 2ⁿ⁻¹-1. Single zero. Negation: invert all bits, add 1. Advantage: addition works identically for signed and unsigned.

Virtual Memory: System providing each process a private, large address space using page-level mapping to physical memory. Enables isolation, sharing, and memory beyond physical RAM size.

Von Neumann Architecture: Computer architecture with single shared memory for instructions and data, connected to CPU via a single bus. Most general-purpose computers follow this model (with cache-level Harvard optimization).

W

Write-Back: Cache write policy where writes update only the cache; dirty blocks written to next level only on eviction. Reduces bus traffic. Requires dirty bit per cache line.

Write-Through: Cache write policy where every write updates both cache and next level simultaneously. Simple but generates high bus traffic. Often paired with write buffer to hide latency.