COA Notes
Complex Instruction Set Computer architecture, design philosophy, and implementation details.
Introduction
CISC (Complex Instruction Set Computer) is a processor design philosophy where each instruction can perform multiple low-level operations — memory access, arithmetic, and storage — all in a single instruction. Think of it this way: in CISC, you can say "add the number at memory address X to register A and store the result back at address X" in one instruction. In RISC, that same operation would take three separate instructions. CISC was the dominant design philosophy from the 1960s through the 1980s, and the x86 architecture (CISC) still powers most desktop and server computers today.
Design Philosophy
The Original Motivation
In the 1960s-1970s, CISC design made perfect sense because:
- Memory was expensive and slow: Complex instructions meant fewer instructions per program → fewer memory accesses for instruction fetching → smaller programs → less expensive memory needed
- Compilers were primitive: Hardware designers thought complex instructions would close the "semantic gap" between high-level languages and machine code
- Microcode was flexible: Microprogrammed control units made it easy to add complex instructions without redesigning hardware
The Semantic Gap
CISC tried to match hardware instructions to high-level language constructs:
| for loop | LOOP instruction |
| procedure call | CALL (saves regs, adjusts SP, jumps) |
| string copy | REP MOVSB (copies entire strings) |
| polynomial evaluation | POLY instruction (VAX) |
| array bounds check | INDEX instruction (VAX) |
The idea was that if hardware could directly execute high-level constructs, programs would be faster. This turned out to be partially wrong — compilers rarely used the complex instructions.
CISC Characteristics
Variable-Length Instructions
| │ NOP | 1 byte (0x90) │ |
| │ PUSH EAX | 1 byte (0x50) │ |
| │ MOV EAX, 42 | 5 bytes (0xB8 + 4-byte immediate) │ |
| │ ADD [EBX+ECX*4+disp32], imm32 | 10+ bytes │ |
| │ With prefixes | up to 15 bytes per instruction │ |
Variable length gives excellent code density (programs use less memory) but makes decoding complex — the CPU cannot know where one instruction ends and the next begins without examining bytes sequentially.
Complex Addressing Modes
CISC processors support many addressing modes, often allowing memory operands directly in arithmetic instructions:
| Mode | Example (x86) | Effective Address |
|---|---|---|
| Immediate | ADD EAX, 5 | Operand in instruction |
| Direct | MOV EAX, [1000h] | Memory[1000h] |
| Register Indirect | MOV EAX, [EBX] | Memory[EBX] |
| Base + Displacement | MOV EAX, [EBP+8] | Memory[EBP+8] |
| Base + Index×Scale + Disp | MOV EAX, [EBX+ECX*4+12] | Memory[EBX+ECX×4+12] |
| Auto-increment | LODSB | Memory[ESI], ESI++ |
| Memory Indirect | JMP [address] | Memory[Memory[address]] |
Memory-to-Memory Operations
Unlike RISC (load/store architecture), CISC allows operations directly on memory:
Multi-Cycle Instructions
CISC instructions take varying numbers of clock cycles:
| Instruction Type | Typical Cycles (8086) | Typical Cycles (Modern x86) |
|---|---|---|
| Register-Register | 2-3 | 1 (as micro-op) |
| Register-Memory | 8-12 | 4-5 (includes cache access) |
| String operations | 9+ per element | 1 per element (optimized) |
| Multiply | 70-160 | 3-5 |
| Divide | 80-190 | 20-40 |
Microprogrammed Control
CISC processors typically use microprogrammed control units:
| Control Memory | (Microcode ROM) | |
|---|---|---|
| Addr 0: μop1 | ──→ Control signals for T1 | |
| Addr 1: μop2 | ──→ Control signals for T2 | |
| Addr 2: μop3 | ──→ Control signals for T3 | |
| ... |
Advantages of microcode:
- Easy to add new instructions (just add microcode sequences)
- Easy to fix bugs (update microcode ROM, even in the field)
- Can implement very complex instructions
Disadvantages:
- Slower than hardwired logic (extra level of interpretation)
- Microcode memory takes die area
- Complex instructions rarely used by compilers
The VAX: Peak CISC
The DEC VAX (1977) represents the extreme of CISC philosophy:
- Over 300 instructions
- 16 addressing modes applicable to almost any operand
- Variable-length instructions (1-54 bytes!)
- Instructions like POLY (polynomial evaluation) and CALLS (full procedure call with register saving)
- Memory-to-memory operations for all arithmetic
The VAX was elegant but impossible to pipeline efficiently. This realization led directly to the RISC revolution.
CISC in Modern Processors
The Translation Approach (Intel since 1995)
Modern x86 processors solve the pipelining problem by translating CISC instructions to RISC-like micro-ops internally:
| Programmer sees | ADD [EBX+8], ECX (one CISC instruction) |
| Hardware executes | μop1: LOAD temp, [EBX+8] (RISC-like) |
| μop2 | ADD temp, temp, ECX (RISC-like) |
| μop3 | STORE [EBX+8], temp (RISC-like) |
This gives backward compatibility (CISC surface) with pipelining efficiency (RISC core).
Why CISC Persists
Despite RISC's architectural advantages, x86 (CISC) dominates desktops and servers because:
- Software ecosystem: Billions of lines of compiled x86 code cannot be rewritten
- Transistor budget: Modern chips have billions of transistors — decode complexity is a tiny fraction
- Code density: x86 programs are 20-30% smaller than ARM equivalents (saves I-cache)
- Investment: Intel/AMD spend $10B+ annually on x86 optimization
CISC vs RISC Summary
| Aspect | CISC | RISC |
|---|---|---|
| Instructions | Complex, many types | Simple, few types |
| Length | Variable (1-15+ bytes) | Fixed (4 bytes) |
| Cycles/instruction | Variable (1-100+) | Mostly 1 |
| Memory access | Any instruction can access memory | Only LOAD/STORE |
| Registers | Fewer (8-16 architectural) | More (32+) |
| Control unit | Microprogrammed | Hardwired |
| Code size | Smaller | Larger |
| Pipelining | Difficult (but solved with translation) | Natural |
| Decode | Complex | Simple |
| Power efficiency | Lower | Higher |
Key Takeaways
- CISC was designed when memory was expensive — complex instructions reduce program size and memory fetches
- Variable-length instructions and complex addressing modes make decoding hard, which made early CISC processors difficult to pipeline
- Modern CISC (x86) internally translates to RISC-like micro-ops — getting the best of both worlds
- The semantic gap idea (hardware matching high-level languages) was mostly wrong — compilers use simple instruction sequences regardless
- CISC persists primarily due to software backward compatibility and the massive x86 ecosystem
- The CISC vs RISC distinction has blurred — modern processors from both camps use similar internal techniques
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