Data Hazards

Introduction

Data hazards are the most frequently occurring pipeline hazards. They happen whenever an instruction needs data that a previous instruction hasn't finished producing yet. The pipeline is moving so fast that instruction N+1 might try to read a register before instruction N has written its result there. This chapter dives deep into the types of data hazards, how hardware detects them, and the elegant forwarding solution that eliminates most stall cycles.

Types of Data Dependencies

RAW (Read After Write) — True Dependency

The most common and significant. Instruction j needs to READ a value that instruction i will WRITE:

This is a "true" dependency — j genuinely needs i's result to proceed correctly.

WAW (Write After Write) — Output Dependency

Two instructions write the same register — order must be preserved:

Not a problem in simple in-order pipelines (instructions naturally complete in order), but critical in out-of-order and superscalar processors.

WAR (Write After Read) — Anti-Dependency

Instruction j writes a register that instruction i reads:

Also not a problem in simple in-order pipelines but relevant in out-of-order execution.

RAW Hazard in the Pipeline (Detailed)

Consider this sequence in a 5-stage pipeline:

The SUB reads R1 in cycle 3, but ADD doesn't write R1 until cycle 5. Without intervention, SUB gets the OLD value of R1.

Multiple Instructions Affected

Detecting Data Hazards

Hardware detects hazards by comparing register fields:

This comparison happens in dedicated hazard detection hardware every cycle.

Solution 1: Stalling

The simplest solution — freeze the pipeline until the data is ready:

The pipeline control inserts "bubbles" (NOP-equivalent) for 2 cycles. Simple but wastes cycles.

Solution 2: Forwarding (Bypassing)

The key insight: the result is COMPUTED in EX (cycle 3 for ADD), even though it's not officially WRITTEN to the register file until WB (cycle 5). Why not route it directly?

With forwarding:

Forwarding Hardware

Multiplexers at ALU inputs select between:

• Normal register file output
• Forwarded value from EX/MEM pipeline register
• Forwarded value from MEM/WB pipeline register

The hazard detection unit controls these MUXes.

Load-Use Hazard (Forwarding Can't Fully Solve)

One case where forwarding alone isn't enough:

Solution: Load-Use Stall + Forward

Insert ONE bubble, then forward from MEM/WB:

One stall cycle is unavoidable for load-use hazards (hardware interlock).

Compiler Optimization: Load Scheduling

Good compilers reorder instructions to fill the stall slot:

Key Takeaways

1. Data hazards occur when instructions have register dependencies that the pipeline can't resolve in time
2. RAW (Read After Write) is the most critical — true data dependency
3. Forwarding/Bypassing eliminates most RAW hazards by routing results directly to where they're needed
4. Load-use hazard requires one mandatory stall cycle (load produces data one cycle later than ALU ops)
5. Hardware hazard detection compares register fields across pipeline stages
6. Compilers help by reordering independent instructions to fill stall slots
7. Forwarding is implemented with multiplexers at ALU inputs controlled by hazard detection logic