Instruction Execution

Introduction

Every single thing your computer does — from displaying a character to calculating a spreadsheet formula — boils down to instructions being executed one after another (or in parallel in modern CPUs). But what exactly happens when an instruction executes? It is not magic — it is a precise sequence of micro-operations involving registers, buses, the ALU, and control signals. Understanding instruction execution at this level transforms you from someone who "uses" computers to someone who truly understands them. Let's trace the complete journey of an instruction from memory to completion.

The Instruction Cycle

Every instruction goes through a fundamental cycle:

Phase 1: Fetch

The fetch phase brings the instruction from memory into the CPU:

In RTL notation:

Each T represents one clock cycle. After fetch, the IR contains the complete instruction and the PC points to the next instruction.

Phase 2: Decode

The control unit examines the opcode field of the IR and determines:

1. What operation to perform
2. Where the operands are (registers? memory? immediate?)
3. Which control signals to activate

For a hardwired control unit, the opcode feeds into a decoder circuit. For a microprogrammed unit, it indexes into a control memory to retrieve the microinstruction sequence.

Phase 3: Execute

This phase varies dramatically based on the instruction type. Let's trace several examples.

Detailed Execution Examples

Example 1: ADD R1, R2, R3 (Register-to-Register Add)

This instruction means: R1 ← R2 + R3

Total: 7 clock cycles for one instruction.

Example 2: LOAD R1, [Address] (Memory Load)

This instruction means: R1 ← Memory[Address]

Notice this takes an extra memory access compared to register operations — this is why load/store operations are slower.

Example 3: STORE R1, [Address] (Memory Store)

Example 4: BEQ Target (Branch if Equal/Zero)

Branch instructions are special — they modify the PC, changing the flow of execution. This is why branches cause problems in pipelined processors (the fetch stage already fetched the wrong next instruction).

Example 5: CALL Subroutine (Function Call)

The saved PC value is the address of the instruction AFTER the CALL, so when RET executes, it can return to the correct location.

Control Signals During Execution

Each micro-operation requires specific control signals to be asserted:

The control unit generates these signals in the correct sequence. This is the fundamental job of the control unit — timing and sequencing of control signals.

Timing Diagram

Here is how an ADD instruction looks on a timing diagram:

Interrupt Handling During Execution

What happens if an interrupt arrives mid-instruction?

1. CPU completes the current instruction (instructions are atomic)
2. CPU saves state: PC, flags, registers pushed to stack
3. CPU acknowledges the interrupt
4. Interrupt vector loaded into PC
5. ISR (Interrupt Service Routine) executes
6. ISR ends with RTI (Return from Interrupt)
7. Original state restored, execution resumes

Multi-Cycle vs Single-Cycle Execution

Single-Cycle Design

• Every instruction completes in one (long) clock cycle
• Clock period = longest instruction time
• Simple but wasteful — fast instructions (ADD) must wait as long as slow ones (LOAD)

Multi-Cycle Design

• Instructions take variable number of shorter clock cycles
• Fast instructions take fewer cycles
• Hardware shared across cycles (one ALU used in different phases)
• More complex control but better resource utilization

Pipelined Design

• Multiple instructions overlap — each in different phase
• One instruction completes per cycle (in steady state)
• Best throughput but introduces hazards

Real-World Observation

When you run a program and it seems slow, here is what might be happening at the instruction execution level:

• Cache miss: A LOAD instruction that would normally take 4 cycles takes 100+ cycles waiting for main memory
• Branch misprediction: The pipeline fetched and partially executed 15-20 wrong instructions that must be flushed
• Data dependency: One instruction waits for a previous instruction's result — pipeline stalls

Modern CPUs execute 4-6 billion instructions per second. Each one goes through this fetch-decode-execute cycle, just incredibly fast and overlapped.

Key Takeaways

1. Every instruction goes through Fetch → Decode → Execute, broken into micro-operations
2. The control unit generates timed control signals that choreograph data movement between registers, ALU, and memory
3. Register operations are faster than memory operations because no memory access is needed in the execute phase
4. Branch instructions modify the PC, redirecting the sequential flow — this is fundamental to all decision-making in programs
5. Interrupts are checked between instructions — the CPU always completes the current instruction before handling an interrupt
6. The number of clock cycles per instruction varies by instruction type — this is what CPI measures as an average