Processor Registers

Introduction

Registers are the fastest storage locations in a computer — they sit inside the CPU itself and can be accessed in a single clock cycle (or even less in pipelined designs). While your computer might have gigabytes of RAM, it only has a handful of registers (typically 16-32 general-purpose ones). These few registers are where the actual computational action happens — data must be loaded into registers before the ALU can operate on it, and results go back into registers before being stored to memory.

Why Registers?

The memory hierarchy creates a fundamental problem: memory is slow relative to the CPU. Even cache takes several cycles to access. Registers solve this by providing instant-access storage for the most immediately needed data.

Speed comparison:

• Register access: ~0 cycles (available same cycle)
• L1 Cache: ~3-4 cycles
• L2 Cache: ~10-12 cycles
• Main Memory: ~100+ cycles

Programs that keep frequently-used values in registers run dramatically faster than those that constantly access memory.

Categories of Registers

1. General Purpose Registers (GPR)

Used by programmers/compilers to hold temporary data and operands:

• Can store data values, addresses, or intermediate results
• Number varies: 8 (x86-32), 16 (x86-64, ARM), 32 (MIPS, RISC-V)
• Width matches processor word size (32 or 64 bits)

Examples:

• x86-64: RAX, RBX, RCX, RDX, RSI, RDI, R8-R15
• ARM: R0-R12
• RISC-V: x0-x31

2. Program Counter (PC)

• Holds the address of the next instruction to be fetched
• Automatically incremented after each fetch
• Loaded with a new value on branch/jump instructions
• Also called Instruction Pointer (IP) in x86

3. Instruction Register (IR)

• Holds the currently executing instruction
• Loaded during the fetch phase
• Fed to the control unit decoder
• Not directly accessible by programs

4. Stack Pointer (SP)

• Points to the top of the system stack in memory
• Automatically updated by PUSH and POP instructions
• Used for function calls (saving return addresses), local variables, and parameter passing
• The stack grows downward in most architectures (SP decreases on PUSH)

5. Status Register / Flags Register (PSW)

Contains individual condition code bits set by the ALU:

• Z (Zero): Last result was zero
• N (Negative): Last result was negative
• C (Carry): Unsigned arithmetic overflow
• V (Overflow): Signed arithmetic overflow
• Plus system flags: Interrupt enable, supervisor mode, etc.

6. Memory Address Register (MAR)

• Holds the address for the next memory access
• Connected directly to the address bus
• Not visible to programmers (internal to CPU)

7. Memory Buffer Register (MBR / MDR)

• Holds data being transferred to/from memory
• Connected to the data bus
• Temporarily buffers data during read/write operations
• Also called Memory Data Register (MDR)

8. Index Registers

• Used in indexed addressing modes
• Hold an offset that's added to a base address
• Useful for array access: base + index × element_size

9. Base Registers / Segment Registers

• Hold base addresses for memory segments
• Used in memory management and protection
• x86 examples: CS (Code Segment), DS (Data Segment), SS (Stack Segment)

Register Organization in Real Processors

x86-64 Registers

ARM (AArch64) Registers

RISC-V Registers

Register Visibility

Register Windowing (SPARC)

The SPARC architecture uses register windows — a novel approach where each function call gets its own set of registers, overlapping with the caller's for parameter passing:

• Avoids saving/restoring registers on function calls
• Large register file (128+ registers) with only 32 visible at a time
• Window pointer rotates on call/return

Key Takeaways

1. Registers are the fastest storage — zero-cycle access within the CPU
2. General purpose registers hold operands and results for computation
3. PC tracks the next instruction; IR holds the current instruction
4. SP manages the stack for function calls and local data
5. Status/Flags register records ALU result conditions for conditional branches
6. MAR/MBR are internal registers for memory communication (not programmer-visible)
7. Register count is a key architectural trade-off: more registers reduce memory accesses but increase instruction size