Forwarding Techniques

Introduction

Forwarding (also called bypassing) is the single most important technique for maintaining pipeline performance in the presence of data hazards. Without forwarding, a 5-stage pipeline would stall 2 cycles for nearly every instruction that depends on the previous one — destroying most of the pipelining benefit. Forwarding adds hardware paths that route results directly from where they are produced to where they are needed, without waiting for the writeback stage. Think of it as a shortcut: instead of waiting for a result to travel all the way back to the register file and then be read again, we intercept it mid-journey.

The Problem Forwarding Solves

Consider this instruction sequence:

Without forwarding:

I2 must wait 2 cycles for R1 to be written to the register file (end of WB) before it can read R1 (in ID). This 2-cycle stall occurs for almost every dependent instruction pair — devastating for performance.

With forwarding:

Zero stalls! The ALU result from I1's EX stage is forwarded directly to I2's EX stage input.

Forwarding Paths

EX-to-EX Forwarding (Most Common)

The result from one instruction's EX stage is forwarded to the very next instruction's EX stage:

Condition for activation:

MEM-to-EX Forwarding

The result from the MEM stage is forwarded to an instruction that is 2 stages behind:

Condition:

The last condition ensures EX-EX takes priority (more recent value) over MEM-EX when both could forward.

Load-to-EX Forwarding (MEM-EX for Loads)

Loads produce results at the end of MEM stage. Even with forwarding, there is a 1-cycle gap:

After the stall, MEM-EX forwarding delivers the loaded value:

Hardware Implementation

Forwarding Unit

Forwarding Multiplexers

Each ALU input gets a multiplexer. The forwarding unit controls the select lines.

Complete Example with Multiple Hazards

Pipeline diagram:

Forwarding paths active:

• Cycle 5: I2 gets R1 from MEM/WB (load forwarding after stall)
• Cycle 6: I3 gets R2 from EX/MEM of I2 (EX-EX)
• Cycle 7: I4 gets R2 from MEM/WB of I2 (MEM-EX) and R4 from EX/MEM of I3 (EX-EX)
• Cycle 8: I5 gets R6 from EX/MEM of I4 (EX-EX), R1 from register file (written in cycle 5)

Forwarding Cannot Solve Everything

Forwarding eliminates stalls for:

• ALU → ALU (any instruction followed by dependent instruction)
• ALU → Store address calculation
• ALU → Branch comparison

Forwarding CANNOT eliminate:

• Load-use: Always 1 stall (data not available until end of MEM)
• Control hazards: Branch outcome not known until EX — forwarding does not help here

Performance Impact

Without forwarding (stall for every RAW hazard):

With full forwarding:

Forwarding improves CPI from 1.80 to 1.075 — a 67% reduction in stall cycles.

Key Takeaways

1. Forwarding routes results from pipeline registers directly to where they are needed, bypassing the register file writeback-then-read delay
2. EX-EX forwarding handles the most common case: ALU result needed by the immediately next instruction
3. MEM-EX forwarding handles cases where the result is needed 2 instructions later
4. Load-use hazards always require 1 stall because the data is not available until end of MEM stage — forwarding cannot travel backward in time
5. The forwarding unit is pure combinational logic — it adds no pipeline stages, only multiplexers and comparators
6. Forwarding reduces average CPI from ~1.8 to ~1.07 — recovering most of the pipeline speedup that hazards would otherwise destroy