CPU Architecture

Introduction

The CPU (Central Processing Unit) is the most complex and fascinating component in a computer. It's a marvel of engineering — billions of transistors organized into functional units that work together to execute billions of instructions every second. Understanding CPU architecture means understanding how registers, the ALU, control unit, and internal buses are organized to form a complete processing engine.

CPU Internal Organization

The CPU has two main paths:

• Datapath: The hardware that performs operations on data (registers, ALU, internal buses)
• Control Path: The hardware that tells the datapath what to do and when (control unit, timing circuits)

Types of CPU Organization

Single Accumulator Organization

• All operations use a single register called the Accumulator (AC)
• Instructions have the form: OPERATION address
• The AC is always one implicit operand
• Example: ADD X means AC ← AC + M[X]
• Simple but requires many memory accesses (load/store for every operation)

General Register Organization

• Multiple registers available for operands and results
• Instructions specify registers: ADD R1, R2, R3 means R1 ← R2 + R3
• Reduces memory accesses (operands stay in registers)
• Most modern processors use this approach
• Faster but instructions need more bits to specify registers

Stack Organization

• Operands are pushed onto and popped from a stack
• Operations implicitly use the top of stack
• Example: PUSH A, PUSH B, ADD → top of stack = A + B
• Compact instructions (no operand addresses needed)
• Used in some calculators and the Java Virtual Machine

Register File Design

The register file is a small, fast memory inside the CPU:

Structure

Specifications

• Number of registers: 8 (x86), 16 (ARM), 32 (MIPS, RISC-V)
• Register width: 32 or 64 bits
• Read ports: Usually 2 (supply both ALU inputs simultaneously)
• Write ports: Usually 1 (write one result per cycle)
• Access time: Single cycle (fastest storage in the system)

Why Not More Registers?

• More registers = more bits needed in instructions to specify them
• More registers = larger, slower register file
• Diminishing returns: most programs don't need hundreds of registers simultaneously

The CPU Datapath

Single-Cycle Datapath

Every instruction completes in exactly one clock cycle:

• Simple control but slow (clock must accommodate the slowest instruction)

Multi-Cycle Datapath

Instructions broken into multiple shorter cycles:

• Each phase (fetch, decode, execute, memory, writeback) is one cycle
• Different instructions take different numbers of cycles
• Hardware is shared across phases (one ALU for both address calculation and arithmetic)
• Faster clock, but more cycles per instruction

Pipelined Datapath

Multiple instructions in different phases simultaneously:

• While instruction N is executing, N+1 is decoding, N+2 is fetching
• Maximum throughput: one instruction per cycle (ideally)
• This is the standard approach in all modern processors

Bus Architecture Within the CPU

Single Internal Bus

Only one transfer per cycle. Simple but slow (multi-cycle operations).

Dual Bus

Read two operands simultaneously. Faster.

Triple Bus

Read two operands AND write result in same cycle. Fastest (used in most modern designs).

Instruction Execution Flow

For a register-register ADD (ADD R1, R2, R3):

1. Fetch: IR ← M[PC]; PC ← PC+4
2. Decode: Control unit determines ADD operation; Read R2 and R3 from register file
3. Execute: ALU computes R2 + R3
4. Write Back: Result stored in R1

For a memory LOAD (LOAD R1, offset(R2)):

1. Fetch: IR ← M[PC]; PC ← PC+4
2. Decode: Read R2 (base address)
3. Execute: ALU computes R2 + offset (effective address)
4. Memory: Read data from computed address
5. Write Back: Store loaded data in R1

Key Takeaways

1. CPU architecture encompasses the datapath (registers + ALU + buses) and control path (control unit)
2. Three organizational styles: accumulator (simple), general register (fast), stack (compact)
3. General register organization dominates modern processors due to reduced memory traffic
4. The register file provides fast, multi-port access to operands
5. Single-cycle, multi-cycle, and pipelined are the three main datapath implementation strategies
6. Internal bus width and port count directly affect how many operations happen per cycle
7. Modern CPUs use pipelined triple-bus designs for maximum throughput