Addressing Modes

Introduction

When an instruction says "add this value" — where IS "this value"? It might be right there in the instruction, or in a register, or in memory at some address, or in memory at an address stored in ANOTHER memory location. Addressing modes define the different ways an instruction can specify the location of its operands. They're one of the most important aspects of an ISA because they determine how flexible and efficient programs can be in accessing data.

Why Multiple Addressing Modes?

Different situations call for different approaches:

• Constants: The value is known at compile time — embed it in the instruction
• Variables: Located at a fixed memory address
• Array elements: Base address + variable index
• Pointers: Follow a chain of memory addresses
• Stack data: Access relative to the stack pointer

Immediate Addressing

The operand value is part of the instruction itself:

Advantages: No memory access needed (fastest), good for constants Disadvantages: Limited value range (constrained by field width) Use case: Constants, initializations, loop increments

Register Addressing

The operand is in a CPU register:

Advantages: Very fast (register access), short address field (3-5 bits) Disadvantages: Limited number of registers Use case: Most common mode in RISC — keep data in registers

Direct (Absolute) Addressing

The instruction contains the memory address of the operand:

Advantages: Simple, straightforward Disadvantages: Limited address range, inflexible for dynamic data Use case: Global variables at fixed locations

Indirect Addressing

The instruction contains the address of a memory location that CONTAINS the actual address:

Advantages: Enables pointers, dynamic memory access Disadvantages: TWO memory accesses (slow) — one to get the address, one to get the data Use case: Pointer dereferencing, linked data structures

Register Indirect Addressing

A register contains the memory address of the operand:

Advantages: Only one memory access, flexible (register can change) Disadvantages: Extra register used for address Use case: Pointer dereferencing, array traversal (increment register through elements)

Base + Offset (Displacement) Addressing

Effective address = register value + constant offset:

Advantages: Access fields within structures, stack variables, array elements Disadvantages: Offset range limited by field size Use case: Structure field access (struct.field), stack frames (SP + offset)

This is the most common addressing mode in modern RISC architectures. ARM, MIPS, and RISC-V use it extensively.

Indexed Addressing

Effective address = base address + index register (index often scaled):

Advantages: Natural for array access with variable index Disadvantages: Requires index register management Use case: Array access: array[i] → base + i × element_size

PC-Relative Addressing

Effective address = PC + offset:

Advantages: Position-independent code (relocatable), branch targets nearby Disadvantages: Limited range (offset field size) Use case: Branch instructions, position-independent code

Stack Addressing (Implied)

Operand is implicitly at the top of stack:

Advantages: Very compact instructions Disadvantages: Limited flexibility Use case: Stack-based architectures, function calls

Auto-Increment and Auto-Decrement

The register is automatically updated after/before the access:

Advantages: Efficient for array traversal and stack operations Use case: Walking through arrays, implementing PUSH/POP

Summary Comparison

Key Takeaways

1. Addressing modes define how instructions locate their operands
2. Immediate (constant in instruction) and register (value in register) are fastest — no memory access
3. Direct specifies a fixed memory address; indirect uses a pointer
4. Base + offset is the dominant mode in RISC — handles structures, stacks, and arrays
5. PC-relative enables position-independent code and nearby branches
6. RISC architectures use few modes (register, immediate, base+offset); CISC has many complex modes
7. More addressing modes = more flexible software but more complex hardware decoding