x86 Architecture

Introduction

The x86 architecture is the most commercially successful instruction set in computing history. Born in 1978 with the Intel 8086 and continuously extended for over 45 years, it powers virtually every desktop, laptop, and server on the planet. Despite being a CISC architecture with decades of backward compatibility burden, x86 processors achieve the highest single-thread performance available. Understanding x86 helps you comprehend why modern processors are designed the way they are — the compromises, the clever engineering, and the relentless pursuit of backward compatibility.

Historical Evolution

Each generation added new features while maintaining complete backward compatibility with every previous generation. A program compiled for the 8086 in 1978 still runs on a 2024 processor.

Register Set

General-Purpose Registers (x86-64)

The nested naming (RAX contains EAX contains AX contains AH:AL) reflects the historical growth from 8-bit to 64-bit.

Special Registers

• RIP (Instruction Pointer): Address of next instruction (64-bit)
• RFLAGS: Status flags (ZF, CF, SF, OF, etc.) + control flags (DF, IF, TF)
• Segment Registers: CS, DS, SS, ES, FS, GS (mostly vestigial in 64-bit mode; FS/GS used for thread-local storage)

SIMD Registers

Instruction Set Characteristics

Variable-Length Instructions

x86 instructions range from 1 to 15 bytes:

This variable length makes decoding complex — the CPU cannot know instruction boundaries without examining bytes sequentially. This is the primary cost of backward compatibility.

Instruction Format

ModR/M byte: Encodes register/memory operand combinations SIB byte: Scale-Index-Base for complex addressing (base + index×scale + displacement)

Rich Addressing Modes

x86 supports complex addressing in a single instruction:

This addressing flexibility means one x86 instruction often replaces 2-3 RISC instructions.

Operating Modes

Real Mode (8086 compatible)

• 16-bit operation, 1 MB address space
• No memory protection, no paging
• CPU boots in this mode
• Used by BIOS/bootloader

Protected Mode (80386+)

• 32-bit operation, 4 GB address space
• Memory protection (segmentation + paging)
• Privilege levels (Ring 0-3)
• Used by 32-bit operating systems

Long Mode (x86-64)

• 64-bit operation, 48-bit virtual addresses (256 TB)
• 4-level page tables (5-level for 57-bit in newer CPUs)
• Mandatory paging (segmentation mostly disabled)
• Used by modern 64-bit operating systems

Internal Micro-Architecture

The CISC-to-RISC Translation

Since the Pentium Pro (1995), all x86 processors internally translate complex CISC instructions into simple micro-ops (μops):

Simple instructions (MOV, ADD between registers) translate 1:1. Complex instructions may generate 4-100+ μops from a microcode ROM.

Why This Design?

The front-end presents a CISC face to software (backward compatibility), but the back-end executes RISC-like μops (efficient pipelining, out-of-order execution). This is why x86 processors are competitive with ARM in performance — internally they are RISC.

Key x86 Extensions

x87 Floating Point (1980)

• 8 FP registers in a stack (ST0-ST7)
• 80-bit extended precision
• Legacy: replaced by SSE/AVX for most uses

MMX/SSE/AVX (SIMD)

• Process multiple data elements in parallel
• SSE: 4 floats simultaneously (128-bit)
• AVX2: 8 floats or 32 bytes simultaneously (256-bit)
• AVX-512: 16 floats or 64 bytes simultaneously (512-bit)
• Critical for: multimedia, scientific computing, AI inference

x86-64 (AMD64)

AMD's 64-bit extension added:

• 64-bit registers and addresses
• 8 additional general-purpose registers (R8-R15)
• 8 additional XMM registers (XMM8-XMM15)
• RIP-relative addressing (position-independent code)
• Red zone (128 bytes below RSP that can be used without adjusting SP)

x86 vs ARM: The Great Debate

Real-World Impact

When you run a program on your laptop:

• Your C++ code compiles to x86-64 instructions
• Those instructions are fetched and decoded into micro-ops (3-6 μops per cycle from cache)
• The out-of-order engine executes 4-6 μops per cycle on multiple execution units
• Branch prediction ensures the pipeline stays full (97%+ accuracy)
• The memory hierarchy (L1/L2/L3/RAM) feeds data at the right time

The entire complexity of x86 decoding, translation, and out-of-order execution happens in hardware — the programmer sees only simple instructions and fast execution.

Key Takeaways

1. x86's 45-year backward compatibility is both its greatest strength (massive software ecosystem) and its greatest burden (decode complexity)
2. Variable-length instructions require complex decode logic — consuming die area and power that ARM avoids
3. Internal micro-op translation means x86 is RISC inside, CISC outside — the best of both worlds
4. Register naming (RAX/EAX/AX/AH/AL) reflects the historical 8→16→32→64-bit evolution
5. SIMD extensions (SSE/AVX/AVX-512) provide massive parallelism for data-intensive workloads
6. Despite efficiency disadvantages, x86's massive out-of-order execution window and clock speeds deliver the highest absolute single-thread performance available