COA Notes
Assembly language addressing techniques and modes for accessing data in memory.
Introduction
Every assembly instruction that works with data needs to know where that data lives — is it in a register, embedded in the instruction itself, or somewhere in memory? Addressing techniques (or addressing modes) are the different ways a CPU can locate operands. Mastering these is essential for writing efficient assembly code and understanding how compilers generate machine code. Each mode has specific use cases: immediate for constants, register for speed, indexed for arrays, and indirect for pointers and dynamic data structures.
Why Multiple Addressing Modes?
Different programming patterns need different access methods:
| int x = 42; | Immediate (constant value) |
| int y = x; | Register (variable in register) |
| int z = array[i]; | Indexed (base + offset) |
| int w = *ptr; | Register Indirect (pointer dereference) |
| int v = **ptr; | Indirect (pointer to pointer) |
| node->next->data | Multiple indirection |
If the CPU only had one addressing mode, many of these would require multiple instructions. Rich addressing modes reduce instruction count.
The Seven Core Addressing Modes
1. Immediate Addressing
The operand value is part of the instruction itself:
; MIPS
li $t0, 100 ; $t0 = 100 (value encoded in instruction)
addi $t1, $t0, 25 ; $t1 = $t0 + 25
; x86
mov eax, 42 ; eax = 42
add ebx, 0xFF ; ebx = ebx + 255Use cases: Constants, loop bounds, bit masks, initial values. Limitation: Value size limited by instruction field width (16-bit in MIPS I-type).
2. Register Addressing
Operand is in a CPU register:
; MIPS
add $t0, $t1, $t2 ; All operands in registers
move $t3, $t0 ; Register-to-register
; x86
add eax, ebx ; eax = eax + ebx
xor ecx, ecx ; ecx = 0 (common idiom)Use cases: All computation in RISC, temporary values, loop counters. Limitation: Limited number of registers (16-32).
3. Direct (Absolute) Addressing
Instruction contains the full memory address:
Use cases: Global variables at fixed addresses, memory-mapped I/O. Limitation: Address field limits addressable range; cannot use variables as addresses.
4. Register Indirect Addressing
Register contains the address of the operand:
Use cases: Pointer dereferencing, traversing linked lists, function pointers. Key insight: This is how C pointers work at the hardware level. *ptr → register indirect.
5. Indexed (Base + Displacement) Addressing
Effective address = Base register + constant offset:
Use cases:
- Stack frame access (local variables at BP + offset)
- Structure/object field access (base + field offset)
- Array with constant index
6. Base + Index Addressing (Scaled)
Effective address = Base + Index × Scale + Displacement:
Use cases: Array element access where index is in a register. Real example: array[i] where array base is in one register and i is in another.
7. PC-Relative Addressing
Effective address = Program Counter + Offset:
; MIPS
beq $t0, $t1, label ; if equal, PC = PC + offset×4
; offset stored as signed 16-bit in instruction
; x86
jmp short label ; PC = PC + signed 8-bit offset
call nearby_function ; PC-relative function callUse cases: All branch instructions, position-independent code (shared libraries). Key advantage: Code can be loaded at any address — offsets are relative, not absolute.
Addressing in Practice: Array Traversal
Here is how addressing modes work together in a real loop:
This single loop uses immediate, register, base+displacement, and PC-relative addressing!
Key Takeaways
- Immediate addressing is fastest (no memory access) — used for constants and small values
- Register addressing is the primary computation mode in RISC — ALU operates only on registers
- Register indirect implements pointers — the fundamental mechanism for dynamic data access
- Base + displacement enables efficient stack frame and structure field access
- Indexed addressing with scaling handles array access — the compiler generates base + index × element_size
- PC-relative addressing enables position-independent code — essential for shared libraries and branch instructions
- RISC architectures have fewer modes (3-5) keeping decode simple; CISC has many (12+) for flexibility at the cost of complexity
Exam Focus
Revise definitions, diagrams, examples, and short-answer points for Addressing Techniques.
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