Register Transfer Operations

Introduction

In the previous topic, we learned the notation of Register Transfer Language. Now let's dive into how these transfers actually happen in hardware. How does data get from one register to another? What physical mechanisms enable these transfers? The answer involves buses, multiplexers, three-state buffers, and careful timing — the building blocks that make the CPU's internal data movement possible.

Types of Register Transfers

Direct Transfer

The simplest operation — copy the contents of one register to another:

After this operation, both R1 and R2 contain the same value. R1 is unchanged.

Conditional Transfer

Transfer only occurs if a control condition is true:

In RTL: P: R2 ← R1

The hardware implementation: the load signal of R2 is ANDed with condition P. Only when P=1 AND the clock edge occurs does R2 actually accept new data.

Multiple Simultaneous Transfers

Both happen at the same clock edge. This requires independent data paths (or a bus wide enough to support both transfers).

Hardware Implementation of Transfers

Point-to-Point Connections

The simplest approach — direct wires between register outputs and inputs:

Problem: With n registers, you'd need n×(n-1) connections — impractical for large systems.

Bus-Based Transfer System

A common bus is a shared set of wires that all registers can use:

Key rule: Only ONE register drives the bus at any time (multiple readers allowed).

Multiplexer-Based Bus

A multiplexer selects which register's output appears on the bus:

For k registers of n bits each: need k-to-1 MUX, n bits wide.

Three-State Bus

Three-state (tri-state) buffers provide an alternative bus implementation:

Each register has output buffers with three states:

• State 1: Output is logic 0
• State 2: Output is logic 1
• State 3: Output is high-impedance (disconnected — Hi-Z)

Only ONE enable signal is active at a time. The enabled register drives the bus; all others are in Hi-Z state (effectively disconnected).

Advantage over MUX: Simpler for large number of registers; doesn't require large multiplexer circuits.

Memory Transfer Operations

Memory Read

Hardware steps:

1. MAR contents placed on address bus
2. Read control signal asserted
3. Memory places data on data bus
4. Data loaded into MBR on clock edge

Memory Write

Hardware steps:

1. MAR contents placed on address bus
2. MBR contents placed on data bus
3. Write control signal asserted
4. Memory stores the data at the specified address

Bus Structures for Multiple Transfers

Single Bus Architecture

Two-Bus Architecture

Three-Bus Architecture

Timing of Register Transfers

Register transfers are synchronized by the clock:

Setup time: Data must be stable on the bus BEFORE the clock edge Hold time: Data must remain stable briefly AFTER the clock edge Propagation delay: Time for data to travel through combinational logic (MUX, ALU)

All transfers within one clock cycle must complete their propagation within the clock period.

Example: A Simple CPU Data Path

Key Takeaways

1. Register transfers are the fundamental operations inside a CPU
2. Buses (shared wires) connect registers efficiently without point-to-point wiring
3. Multiplexers or three-state buffers control which register drives the bus
4. Only one source can drive a bus at any time; multiple destinations can read
5. Memory transfers use MAR for address and MBR for data
6. Multi-bus architectures (2 or 3 buses) allow parallel operations in one clock cycle
7. All transfers are synchronized to clock edges with setup and hold time requirements