Direct Memory Access (DMA)

Introduction

Even interrupt-driven I/O has a problem: for large data transfers (loading a file, streaming video, network packets), the CPU must handle EVERY word — read from device, write to memory, one word at a time. For a 1 GB file transfer, that's billions of CPU interventions! DMA (Direct Memory Access) solves this by providing a specialized hardware controller that transfers data directly between device and memory WITHOUT CPU involvement. The CPU sets up the transfer and then is free to do other work.

The DMA Concept

Instead of: Device → CPU → Memory (CPU involved in every transfer) DMA does: Device → DMA Controller → Memory (CPU only involved in setup)

DMA Controller Architecture

DMA Transfer Steps

1. CPU programs the DMA controller:

• Starting memory address (where to put/get data)
• Transfer count (how many bytes/words)
• Transfer direction (device→memory or memory→device)
• Transfer mode (burst, cycle-stealing, etc.)

1. CPU tells device to start (or device requests transfer)

1. DMA controller takes over:

• Requests the bus (Bus Request signal)
• CPU grants bus access (Bus Grant signal)
• DMA controller drives address and data buses
• Transfers data directly between device and memory
• Increments address, decrements count each transfer

1. Transfer complete:

• DMA controller releases the bus
• Asserts interrupt to notify CPU "done!"
• CPU reads status register if needed

DMA Transfer Modes

Burst Mode (Block Transfer)

• DMA holds the bus for the ENTIRE transfer
• Fastest for the transfer itself
• CPU is completely locked out until done
• Best for: time-critical transfers where latency matters

Cycle Stealing Mode

• DMA takes the bus for ONE word, then releases
• CPU and DMA alternate bus access word-by-word
• CPU slows down slightly but isn't blocked
• Best for: transfers that don't need to complete quickly

Transparent Mode

• DMA transfers only when CPU isn't using the bus
• Zero impact on CPU performance
• Slowest overall transfer time
• Best for: background transfers where speed doesn't matter

Comparison of I/O Methods

Bus Arbitration for DMA

Since both CPU and DMA need the bus, arbitration is required:

• Bus Request (BR): DMA asks for bus control
• Bus Grant (BG): CPU/arbiter allows DMA to use bus
• Bus Busy (BB): Indicates bus is currently in use

The DMA controller becomes a bus master during its transfers.

Key Takeaways

1. DMA transfers data between device and memory WITHOUT CPU involvement
2. CPU programs DMA (address, count, direction), then is free to do other work
3. DMA controller takes over the bus and handles the entire transfer
4. Three modes: Burst (fastest, blocks CPU), Cycle-stealing (shares bus), Transparent (no impact)
5. After transfer completes, DMA interrupts the CPU to signal completion
6. DMA is essential for high-bandwidth devices (disk, network, GPU)
7. DMA reduces CPU overhead from O(n) per byte to O(1) per transfer