Fetch-Decode-Execute Cycle

Introduction

The fetch-decode-execute cycle is the heartbeat of every processor. Just as your heart beats continuously to keep you alive, the CPU repeats this cycle billions of times per second to keep your computer running. Every single thing your computer does — from displaying a character on screen to computing the trajectory of a rocket — is accomplished through this simple three-step cycle repeated over and over.

The Three Phases

Phase 1: Fetch

The CPU retrieves the next instruction from memory.

What happens:

1. The Program Counter (PC) contains the address of the next instruction
2. This address is placed on the address bus
3. A "memory read" signal is sent via the control bus
4. Memory responds by placing the instruction on the data bus
5. The instruction is loaded into the Instruction Register (IR)
6. The PC is incremented to point to the next instruction

Phase 2: Decode

The control unit figures out what the instruction means.

What happens:

1. The control unit examines the opcode (operation code) field of the instruction
2. It determines what operation to perform (ADD, LOAD, STORE, BRANCH, etc.)
3. It identifies the operands (which registers or memory locations are involved)
4. It generates the sequence of control signals needed for execution

Think of decode as translation: converting the binary instruction code into a series of internal commands.

Phase 3: Execute

The CPU actually performs the operation.

What happens (depends on instruction type):

• Arithmetic/Logic: ALU performs the operation on register contents
• Memory Read: Address is sent to memory, data is loaded into a register
• Memory Write: Data from a register is sent to a memory address
• Branch: PC is loaded with the target address (changes execution flow)
• I/O: Data is transferred to/from an I/O device

Detailed Example: ADD R1, R2, R3

Let's trace "Add the contents of R2 and R3, store result in R1":

Fetch:

Decode:

Execute:

The Instruction Cycle State Diagram

Subcycles and Timing

Each main phase may take multiple clock cycles. A more detailed breakdown:

T1 (Fetch - Address Phase)

• PC contents placed on address bus
• Memory Read signal asserted

T2 (Fetch - Data Phase)

• Wait for memory to respond
• Instruction arrives on data bus
• Instruction loaded into IR
• PC incremented

T3 (Decode)

• Opcode interpreted
• Control signals generated
• Operand addresses calculated (if needed)

T4-T6 (Execute)

• Number of cycles depends on instruction complexity
• Simple register-register: 1 cycle
• Memory access: 2+ cycles (address + data transfer)
• Complex operations (multiply): Multiple cycles

The Role of the Clock

The system clock is a periodic signal that synchronizes all operations:

• Clock period: Time for one cycle (e.g., 0.3 ns for a 3.3 GHz processor)
• CPI (Cycles Per Instruction): Average number of clock cycles per instruction
• CPU Time = Instruction Count × CPI × Clock Period

Interrupts: Breaking the Cycle

Sometimes the normal fetch-decode-execute cycle is interrupted:

1. After each execute phase, the CPU checks for pending interrupts
2. If an interrupt is pending:

• Current state (PC, registers) is saved
• PC is loaded with the interrupt handler address
• The handler code executes (still using fetch-decode-execute!)
• When done, original state is restored and normal execution resumes

Multiple Data Paths

Some instructions require additional cycles for data movement:

Load Instruction (LOAD R1, [address])

1. Fetch the instruction
2. Decode: this is a LOAD; need to read memory
3. Calculate effective address
4. Send address to memory, get data
5. Store data in R1

Store Instruction (STORE R1, [address])

1. Fetch the instruction
2. Decode: this is a STORE; need to write memory
3. Calculate effective address
4. Send address + data from R1 to memory
5. Memory writes the data

Branch Instruction (BEQ label)

1. Fetch the instruction
2. Decode: this is a conditional branch
3. Check the condition (zero flag set?)
4. If true: load target address into PC
5. If false: do nothing (PC already points to next instruction)

Performance Implications

The fetch-decode-execute cycle directly determines performance:

• Instruction throughput: How many instructions complete per second
• Pipeline optimization: Modern CPUs overlap multiple cycles (fetching instruction N+1 while executing instruction N)
• Branch prediction: Guessing which way a branch will go to avoid stalling the fetch phase
• Cache hits: Fetching from cache (1-3 cycles) vs memory (100+ cycles) makes a huge difference

Key Takeaways

1. The fetch-decode-execute cycle is the fundamental operating rhythm of every CPU
2. Fetch retrieves the instruction from memory using the PC address
3. Decode interprets the instruction and generates control signals
4. Execute performs the actual operation (arithmetic, memory access, branch)
5. The cycle repeats billions of times per second (controlled by the clock)
6. Different instructions take different numbers of clock cycles
7. Interrupts can temporarily redirect execution to handle urgent events
8. Modern CPUs pipeline this cycle to execute multiple instructions simultaneously