SR Flip-Flop — Set-Reset Latch and Flip-Flop Complete Guide

SR Latch (Basic)

The SR latch (also called SR flip-flop in some texts) is the most fundamental bistable circuit — it can hold one of two stable states (Q=0 or Q=1) indefinitely.

NOR Gate SR Latch

Truth Table (NOR latch):

Forbidden state: S=R=1 causes both Q=Q̄=0, violating Q ≠ Q̄. When inputs return to S=R=0, the final state is unpredictable (race condition).

NAND Gate SR Latch

Note: NAND latch is active LOW — inputs are inverted compared to NOR latch.

Excitation Table

Interview Questions

Q1: Why is S=R=1 forbidden in the SR flip-flop? When S=R=1 in a NOR latch, both outputs Q and Q̄ are forced to 0 simultaneously, violating the fundamental requirement Q ≠ Q̄. When the inputs return to S=R=0, both gates race to determine the final state — the outcome depends on propagation delays and is unpredictable.

Q2: What is the difference between a latch and a flip-flop? A latch is level-sensitive — it responds to input changes whenever the enable signal is active (CLK=1). A flip-flop is edge-triggered — it only responds at the active clock edge (rising or falling transition). Flip-flops are preferred in synchronous digital design because they provide predictable, glitch-free operation.

Q3: How is the SR flip-flop used as a switch debouncer? Mechanical switches bounce (rapidly open/close) when pressed. By connecting the switch to Set and Reset inputs of a NAND SR latch, the first contact sets the latch firmly to Q=1, and subsequent bounces have no effect. When released, R sets Q=0. The latch filters out all bounces.

Q4: What is the characteristic equation of SR flip-flop? Q(t+1) = S + R̄·Q(t), with constraint S·R = 0 (S and R cannot both be 1 simultaneously).