DE Notes

Synchronous Counters — Design, MOD-N Counter, Up/Down Counter

Complete guide to synchronous counters: 2-bit, 3-bit, 4-bit synchronous counters, MOD-N counter design procedure, up/down counter, BCD counter, excitation equations and Verilog.

Synchronous vs Asynchronous Counters

Property	Synchronous	Asynchronous (Ripple)
Clock	All FFs share same clock	Clock ripples through FFs
Speed	Faster (no ripple delay)	Slower (cumulative delay)
Glitches	No intermediate states	Transient intermediate states
Design	More complex	Simpler
IC examples	74163, 74191	7493, 7490

In synchronous counters: All flip-flops are clocked simultaneously. The next state of each FF is determined by combinational logic.

4-Bit Synchronous Binary Counter

Excitation equations (T flip-flops):

Example

T0 = 1 T1 = Q0 T2 = Q0 · Q1 T3 = Q0 · Q1 · Q2

Pattern: Each bit toggles when all lower bits are 1. This is the ripple carry concept, but done combinationally in advance — no delay.

Count sequence: 0000 → 0001 → ... → 1110 → 1111 → 0000

MOD-N Counter Design Procedure

To build a MOD-N counter (counts 0 to N-1):

Determine number of flip-flops: r = ⌈log₂(N)⌉
Draw state transition table for the N valid states
Remaining 2^r - N states: treat as don't-cares (or reset to 0)
Derive next-state equations using K-maps
Convert to flip-flop excitation equations

Example: MOD-5 counter (0 to 4)

r = 3 flip-flops (2³=8 ≥ 5)

Q2	Q1	Q0	Q2⁺	Q1⁺	Q0⁺
0	0	0	0	0	1
0	0	1	0	1	0
0	1	0	0	1	1
0	1	1	1	0	0
1	0	0	0	0	0
(101,110,111 → don't care or reset 000)

Using D flip-flops (D = Q⁺):

Example

D0 = Q2̄·Q0̄ (from K-map) D1 = Q0̄·Q1 + Q1̄·Q0 = Q1 ⊕ Q0 D2 = Q1·Q0

BCD Counter (MOD-10)

Counts 0000 to 1001 (0–9), resets at 1010 (10).

Example

When Q3Q0 = 1010, reset all to 0000 immediately (using CLR) OR design excitation equations that skip states 1010–1111

IC 7490: BCD counter, separate MOD-2 and MOD-5 sections

Up/Down Counter

Counts up or down based on a direction control input (UP/D̄OWN).

Using JK flip-flops:

When UP=1: count up	JK equations for up-count
When UP=0: count down	JK equations for down-count
Combined	J0 = K0 = 1 (Q0 always toggles)

IC 74191: Synchronous 4-bit up/down counter with load and enable.

IC 74163: 4-Bit Synchronous Counter

Example

┌───────────────────────┐ CLK ────┤ ├─── QA, QB, QC, QD CLR̄ ────┤ 74163 ├─── RCO (ripple carry out) LOAD̄ ───┤ (synchronous clear, │ ENP ────┤ load, enable) │ ENT ────┤ │ A,B,C,D─┤ (parallel load inputs)│ └───────────────────────┘

Features:

Synchronous clear (CLR̄) — resets on next clock edge
Synchronous parallel load (LOAD̄) — loads A,B,C,D on next clock edge
Enable pins ENP, ENT — for cascading
RCO output for cascading multiple 74163s

For MOD-N using 74163: Connect RCO to LOAD̄, preset desired starting count.

Numericals

Q1: Design MOD-6 counter using JK flip-flops.

3 FFs needed. States: 000	001→010→011→100→101→000
Q2Q1Q0	Q2⁺Q1⁺Q0⁺ → J2K2 J1K1 J0K0
000	001 → J2=0,K2=X; J1=0,K1=X; J0=1,K0=X
001	010 → J2=0,K2=X; J1=1,K1=X; J0=X,K0=1
010	011 → J2=0,K2=X; J1=X,K1=0; J0=1,K0=X
011	100 → J2=1,K2=X; J1=X,K1=1; J0=X,K0=1
100	101 → J2=X,K2=0; J1=0,K1=X; J0=1,K0=X
101	000 → J2=X,K2=1; J1=0,K1=X; J0=X,K0=1

Interview Questions

Q1: Why are synchronous counters preferred over ripple counters? Synchronous counters clock all flip-flops simultaneously, so maximum delay = single FF delay + combinational logic (constant, independent of bit count). Ripple counters have delay = n × FF delay (grows with n). Synchronous counters also avoid transient glitch states between counts since all bits change together.

Q2: How many flip-flops are needed for a MOD-12 counter? 2^r ≥ 12 → 2^4 = 16 ≥ 12, so r = 4 flip-flops. Counts 0000 to 1011, skipping/resetting from 1100.

Q3: What is the purpose of the ENP and ENT inputs on IC 74163? Both must be HIGH for the counter to count. ENT also enables the RCO (ripple carry output) when the counter reaches its maximum count. Cascading: connect RCO of lower chip to ENP and ENT of upper chip.

Q4: How do you design a synchronous MOD-N counter using 74163? Method 1 (reset): Detect state N using NAND gate, connect to CLR̄ → resets on next clock. Method 2 (preset): Detect state N-1 using NAND, connect to LOAD̄ → preloads 0000 on next clock. The preset method is preferred for synchronous operation.

Exam Focus

Revise definitions, diagrams, examples, and short-answer points for Synchronous Counters — Design, MOD-N Counter, Up/Down Counter.

Interview Use

Prepare one clear explanation, one practical example, and one common mistake for this Digital Electronics topic.

Search Terms

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DE Notes

Synchronous Counters — Design, MOD-N Counter, Up/Down Counter

Complete guide to synchronous counters: 2-bit, 3-bit, 4-bit synchronous counters, MOD-N counter design procedure, up/down counter, BCD counter, excitation equations and Verilog.

Synchronous vs Asynchronous Counters

Property	Synchronous	Asynchronous (Ripple)
Clock	All FFs share same clock	Clock ripples through FFs
Speed	Faster (no ripple delay)	Slower (cumulative delay)
Glitches	No intermediate states	Transient intermediate states
Design	More complex	Simpler
IC examples	74163, 74191	7493, 7490

In synchronous counters: All flip-flops are clocked simultaneously. The next state of each FF is determined by combinational logic.

4-Bit Synchronous Binary Counter

Excitation equations (T flip-flops):

Example

T0 = 1 T1 = Q0 T2 = Q0 · Q1 T3 = Q0 · Q1 · Q2

Pattern: Each bit toggles when all lower bits are 1. This is the ripple carry concept, but done combinationally in advance — no delay.

Count sequence: 0000 → 0001 → ... → 1110 → 1111 → 0000

MOD-N Counter Design Procedure

To build a MOD-N counter (counts 0 to N-1):

Determine number of flip-flops: r = ⌈log₂(N)⌉
Draw state transition table for the N valid states
Remaining 2^r - N states: treat as don't-cares (or reset to 0)
Derive next-state equations using K-maps
Convert to flip-flop excitation equations

Example: MOD-5 counter (0 to 4)

r = 3 flip-flops (2³=8 ≥ 5)

Q2	Q1	Q0	Q2⁺	Q1⁺	Q0⁺
0	0	0	0	0	1
0	0	1	0	1	0
0	1	0	0	1	1
0	1	1	1	0	0
1	0	0	0	0	0
(101,110,111 → don't care or reset 000)

Using D flip-flops (D = Q⁺):

Example

D0 = Q2̄·Q0̄ (from K-map) D1 = Q0̄·Q1 + Q1̄·Q0 = Q1 ⊕ Q0 D2 = Q1·Q0

BCD Counter (MOD-10)

Counts 0000 to 1001 (0–9), resets at 1010 (10).

Example

When Q3Q0 = 1010, reset all to 0000 immediately (using CLR) OR design excitation equations that skip states 1010–1111

IC 7490: BCD counter, separate MOD-2 and MOD-5 sections

Up/Down Counter

Counts up or down based on a direction control input (UP/D̄OWN).

Using JK flip-flops:

When UP=1: count up	JK equations for up-count
When UP=0: count down	JK equations for down-count
Combined	J0 = K0 = 1 (Q0 always toggles)

IC 74191: Synchronous 4-bit up/down counter with load and enable.

IC 74163: 4-Bit Synchronous Counter

Example

Features:

Synchronous clear (CLR̄) — resets on next clock edge
Synchronous parallel load (LOAD̄) — loads A,B,C,D on next clock edge
Enable pins ENP, ENT — for cascading
RCO output for cascading multiple 74163s

For MOD-N using 74163: Connect RCO to LOAD̄, preset desired starting count.

Numericals

Q1: Design MOD-6 counter using JK flip-flops.

3 FFs needed. States: 000	001→010→011→100→101→000
Q2Q1Q0	Q2⁺Q1⁺Q0⁺ → J2K2 J1K1 J0K0
000	001 → J2=0,K2=X; J1=0,K1=X; J0=1,K0=X
001	010 → J2=0,K2=X; J1=1,K1=X; J0=X,K0=1
010	011 → J2=0,K2=X; J1=X,K1=0; J0=1,K0=X
011	100 → J2=1,K2=X; J1=X,K1=1; J0=X,K0=1
100	101 → J2=X,K2=0; J1=0,K1=X; J0=1,K0=X
101	000 → J2=X,K2=1; J1=0,K1=X; J0=X,K0=1

Interview Questions

Q2: How many flip-flops are needed for a MOD-12 counter? 2^r ≥ 12 → 2^4 = 16 ≥ 12, so r = 4 flip-flops. Counts 0000 to 1011, skipping/resetting from 1100.

Exam Focus

Revise definitions, diagrams, examples, and short-answer points for Synchronous Counters — Design, MOD-N Counter, Up/Down Counter.

Interview Use

Prepare one clear explanation, one practical example, and one common mistake for this Digital Electronics topic.

Search Terms

digital-electronics, digital electronics, digital, electronics, registers, and, counters, synchronous

Continue learning this concept

PreviousSISO Register NextGlossary of Terms — Digital Electronics