RAM — SRAM and DRAM Architecture, Working and Comparison

What is RAM?

RAM (Random Access Memory) is volatile read-write memory — data is lost when power is removed. "Random access" means any memory location can be read or written in the same time (unlike sequential access).

Two main types: SRAM (Static) and DRAM (Dynamic).

DRAM — Dynamic RAM

1T1C DRAM Cell

Operation:

• Data stored as charge on tiny capacitor (1 = charged, 0 = discharged)
• WL = 1: access transistor connects capacitor to bit line
• Read is destructive — charge on capacitor collapses onto bit line
• Sense amplifier detects small voltage, then writes data back (restore)
• Refresh required: Capacitor leaks charge → must be read and rewritten every ~64 ms

Characteristics:

• 1 transistor + 1 capacitor per bit → very high density, low cost
• Slower (10–100 ns access)
• Higher power (refresh cycles)
• Used in: Main memory (RAM DIMMs), GPU framebuffer

SRAM vs DRAM Comparison

Memory Organization

A memory chip is organized as a 2D array:

Row/Column addressing (DRAM): DRAM uses multiplexed addressing — same pins used for row address (RAS) then column address (CAS), halving the number of address pins.

Memory Capacity Formula

DDR Memory Generations

DDR (Double Data Rate) transfers data on both rising and falling clock edges, doubling bandwidth.

Interview Questions

Q1: Why does DRAM need refresh but SRAM doesn't? DRAM stores data as charge on a tiny capacitor. Capacitors gradually leak charge through transistor subthreshold current and junction leakage. After ~64 ms, the stored charge degrades enough to cause read errors. Refresh reads each row and rewrites it to restore full charge. SRAM stores data in a cross-coupled inverter pair — an active circuit that constantly maintains its state as long as power is supplied.

Q2: Why is SRAM faster than DRAM? SRAM access is a single step: assert WL, sense BL differential, read/write. DRAM access requires: row address (RAS), column address (CAS), charge-sharing on bit line, sense amplifier settling, and write-back (for reads). Multiple sequential operations make DRAM 10–100× slower. Additionally, DRAM's sense amplifiers need extra time to detect the small capacitor voltage.

Q3: How many address lines does 4K × 8 RAM require? 4K = 4096 = 2^12. So 12 address lines + 8 data lines + control lines (CS, WE, OE).

Q4: What is RAS and CAS latency? In DRAM, RAS (Row Address Strobe) latency is the time from row address to data available. CAS latency is the time from column address to data available. Lower CAS latency = faster memory. DDR4 typically has CAS latency of 14–20 nanoseconds. Combined: total access time = tRCD + CL × tclk.

Q5: What is SDRAM and how does it differ from regular DRAM? SDRAM (Synchronous DRAM) is synchronized to the system clock, allowing pipelined operations. Regular (asynchronous) DRAM used separate strobe signals and couldn't pipeline. SDRAM can accept a new command every clock cycle. All modern memory (DDR2/3/4/5) is synchronous.