ROM — Types of Read-Only Memory: PROM, EPROM, EEPROM, Flash

What is ROM?

ROM (Read-Only Memory) is non-volatile memory — data is retained when power is removed. Originally truly read-only (mask ROM), modern variants can be reprogrammed electrically.

Mask ROM

Programmed during fabrication — connections (or lack thereof) hardwired into the chip.

Cell structure:

Pros: Lowest cost per bit at high volumes, fastest access Cons: Cannot be reprogrammed, high NRE cost, long lead time

PROM (Programmable ROM)

Shipped with all cells in one state (e.g., all 1s). User programs by "blowing" fuse links.

Fuse cell:

Once blown, fuse cannot be restored — one-time programmable (OTP).

EPROM (Erasable PROM)

Uses floating-gate transistors. Electrons trapped on floating gate change threshold voltage.

Floating gate structure:

Programming (Write 0): Apply high voltage (12–25V) between drain and control gate → hot carrier injection → electrons tunnel onto floating gate → raises Vth → MOSFET remains OFF even when addressed → reads 0.

Erasing: Expose chip through quartz window to UV light (254 nm, ~20 min) → UV energy ejects electrons from floating gate → all cells reset to 1.

Key feature: Quartz window on top of chip for UV exposure.

EEPROM (Electrically Erasable PROM)

Similar to EPROM but uses Fowler-Nordheim tunneling for both write and erase — no UV light needed.

Advantages over EPROM:

• Byte-by-byte erasure (vs bulk erase for EPROM)
• Erase/reprogram without removing from circuit (in-system programming)
• ~10,000 write/erase cycles endurance

Used in: Microcontroller configuration storage, BIOS chips (older), calibration data

Flash Memory

Flash is improved EEPROM with sector-based erase (faster than EEPROM's byte-erase).

Two types:

• NOR Flash: Random byte access, execute-in-place (XIP), slower write/erase
• NAND Flash: Block access, higher density, faster write, no XIP

Applications:

• NOR: Embedded MCU program storage (STM32, ESP32 flash)
• NAND: USB drives, SSDs, SD cards, smartphones (eMMC/UFS)

ROM as Combinational Logic

A ROM can implement any combinational function — each address is a minterm, each data output is a function output.

Example: Implement 4-bit adder S = A + B using ROM

Numerical Example

Q: How many address and data lines does a 8K × 8 ROM have?

Interview Questions

Q1: What distinguishes EPROM from EEPROM? EPROM is erased by UV light exposure through a quartz window and requires removal from circuit. EEPROM is erased electrically, byte-by-byte, without removal. EEPROM is more convenient but more complex and expensive. EPROM has better data retention (>10 years) and is cheaper for high volumes.

Q2: Why does Flash memory need sector erase instead of byte erase? In NAND Flash, cells are arranged in series strings. You cannot selectively apply erase voltage to individual cells without affecting neighbors. The entire string (block) must be erased together. This is a fundamental architectural compromise for high density — fewer connections per cell means fewer control lines but coarser erase granularity.

Q3: What is wear leveling in Flash memory? Flash cells have limited write/erase cycles (~100,000 for SSD). If the same locations were repeatedly written, they would fail quickly. Wear leveling algorithms spread writes uniformly across all flash blocks, extending total device lifetime. SSDs use sophisticated wear leveling to achieve years of reliable operation.

Q4: How is ROM used to implement combinational logic? ROM is essentially a lookup table. An n-input, m-output combinational function requires 2^n × m ROM. Each address corresponds to an input combination; stored data gives the output. This is the basis for LUTs (Look-Up Tables) in FPGAs — each 6-input LUT is a 64×1 ROM.

Q5: What is the endurance specification for EEPROM vs Flash? EEPROM: typically 100,000–1,000,000 write/erase cycles per byte. Flash (NAND): 1,000–100,000 cycles per block depending on technology (SLC > MLC > TLC > QLC in endurance). Flash trades endurance for density.