Memory Management Interview Questions

Introduction

Memory management is a favorite topic in OS interviews because it combines conceptual understanding with numerical problem-solving. Interviewers test whether you understand address translation, can calculate effective access times, know how page replacement algorithms work, and can explain complex concepts like thrashing simply. Master these questions and you will handle any memory-related interview question confidently.

Conceptual Questions

Q1: What is the difference between logical and physical addresses?

Answer: A logical (virtual) address is generated by the CPU during program execution — it represents where the program "thinks" data is located. A physical address is the actual location in RAM hardware. The Memory Management Unit (MMU) translates logical addresses to physical addresses at runtime.

This separation provides two key benefits: (1) programs can be loaded at any physical location without modification (relocation), and (2) each process gets its own independent address space (protection) — process A cannot access process B's memory because their logical addresses map to different physical frames.

Q2: Explain paging. Why does it eliminate external fragmentation?

Answer: Paging divides logical memory into fixed-size blocks called pages and physical memory into same-sized blocks called frames. Any page can be loaded into any available frame — they do not need to be contiguous. The page table tracks which frame holds each page.

External fragmentation occurs when free memory exists but is scattered in small non-contiguous chunks. Paging eliminates this because allocation happens in fixed-size frames — a process needing 4 frames can use any 4 frames anywhere in memory, regardless of their physical arrangement. However, internal fragmentation still exists: the last page of a process may not be completely filled.

Q3: What is a TLB and why is it important?

Answer: The Translation Lookaside Buffer (TLB) is a specialized hardware cache that stores recent page-to-frame mappings. Without a TLB, every memory access requires TWO memory accesses: one to read the page table and one to access the actual data. With a TLB, recently used translations are found immediately.

Modern TLBs have 64-1024 entries and achieve hit ratios above 99% due to locality of reference. The performance impact is dramatic:

The TLB essentially cuts memory access overhead in half for the common case.

Q4: What is demand paging?

Answer: Demand paging means pages are loaded into memory only when accessed — not when the process starts. Initially, all pages are marked "invalid" in the page table. When a process accesses a page not in memory, a page fault occurs:

1. CPU generates address → MMU checks page table → page marked invalid
2. Page fault trap to OS
3. OS finds the page on disk (swap space)
4. OS finds a free frame (or runs page replacement algorithm)
5. OS loads page from disk to frame
6. OS updates page table (mark page as valid with frame number)
7. Restart the instruction that caused the fault

This allows processes to run even when they are larger than available physical memory.

Q5: Explain thrashing. What causes it and how is it solved?

Answer: Thrashing occurs when the system spends more time handling page faults than executing useful instructions. It happens when the total working set size of all active processes exceeds available physical memory.

The vicious cycle: Process page faults → waits for I/O → CPU utilization drops → OS admits more processes (thinking CPU is underused) → even less memory per process → more page faults → repeat.

Solutions:

• Working Set Model: Track each process's active pages; only allow processes whose working sets fit in memory
• Page Fault Frequency: If a process's fault rate exceeds upper threshold, give it more frames; if below lower threshold, take frames away
• Reduce degree of multiprogramming: Suspend some processes to free memory for remaining ones

Numerical Problems

Q6: Calculate physical address from logical address.

Given: Page size = 4KB (4096 bytes), logical address = 13000

Solution:

Q7: Calculate Effective Access Time (EAT) with TLB.

Given: Memory access time = 100ns, TLB access time = 20ns, TLB hit ratio = 95%

Solution:

Without TLB: 200ns. With TLB: 125ns — a 37.5% improvement.

Q8: Page replacement using FIFO and LRU.

Given: 3 frames, reference string: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3

FIFO Solution:

LRU Solution:

Q9: How many bits for page number and offset?

Given: Logical address space = 64KB, page size = 1KB

Solution:

Q10: Calculate page table size.

Given: 32-bit logical address, 4KB page size, each page table entry = 4 bytes

Solution:

This is why multi-level paging exists — the page table itself is too large to keep entirely in memory.

Advanced Questions

Q11: Explain Belady's Anomaly.

Answer: Belady's Anomaly is a counterintuitive phenomenon where increasing the number of page frames INCREASES page faults for FIFO replacement. This happens because FIFO does not follow the "stack property" — the set of pages in memory with n frames is not always a subset of those with n+1 frames.

Example reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

• 3 frames: 9 page faults
• 4 frames: 10 page faults (worse!)

LRU and Optimal never exhibit this anomaly because they are stack algorithms.

Q12: Compare segmentation and paging.

Interview Tips

1. For numerical problems, clearly state the formula before substituting values
2. Always specify whether you mean logical or physical address
3. Remember: more frames generally means fewer page faults (except Belady's Anomaly with FIFO)
4. Practice tracing page replacement algorithms step-by-step — draw the frame table
5. Know the hierarchy: Registers → Cache → TLB → RAM → Disk (speed decreases, size increases)