VLSI Design Notes — B.Tech ECE Sem 4

VLSI Design — Introduction

VLSI (Very Large Scale Integration) — ek single chip pe millions/billions transistors integrate karna.

Generations: | Generation | Transistors/chip | Technology node | |-----------|-----------------|----------------| | SSI | <100 | 1960s | | MSI | 100–3,000 | 1970s | | LSI | 3,000–100,000 | Late 1970s | | VLSI | 100K–1M | 1980s | | ULSI | >1M | 1990s–now | | Modern SoC | Billions | 3–7nm (TSMC, Samsung) |

Design Flow Overview:

Specification → RTL Design (Verilog/VHDL) → Synthesis
→ Placement → Routing → DRC/LVS → Tape-out → Fabrication

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1. CMOS Technology

MOSFET — Metal Oxide Semiconductor FET:

NMOS (n-channel):
- Conducts when Gate = HIGH (1)
- Electrons as carriers
- Faster (higher mobility)

PMOS (p-channel):
- Conducts when Gate = LOW (0)
- Holes as carriers
- Slower

CMOS Inverter — simplest VLSI gate:

VDD ─── PMOS (source)
         │
         ├─── Output
         │
GND ─── NMOS (source)

Input → both gates
Output HIGH when Input LOW (PMOS on, NMOS off)
Output LOW when Input HIGH (NMOS on, PMOS off)

CMOS Static Power:

• Ideal CMOS: zero static power (neither transistor fully on when stable)
• Leakage current exists at nanoscale nodes
• Dynamic power = C × V² × f (switching)

Scaling (Moore's Law): | Node | Year | Gate length | |------|------|-------------| | 1000nm | 1990 | 1μm | | 130nm | 2001 | ~130nm | | 22nm | 2012 | FinFET introduced | | 5nm | 2020 | TSMC | | 3nm | 2022 | Apple M2 |

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2. Logic Gates in CMOS

NAND Gate (CMOS implementation)

NAND = NOT(A AND B)

PMOS network (pull-up — in parallel):
  VDD → PMOS_A (parallel) PMOS_B → Output

NMOS network (pull-down — in series):
  Output → NMOS_A → NMOS_B → GND

Truth Table:
A B | Output
0 0 |   1
0 1 |   1
1 0 |   1
1 1 |   0    ← only 1+1 gives 0

NOR Gate

NOR = NOT(A OR B)

PMOS: in series (pull-up)
NMOS: in parallel (pull-down)

Truth Table:
A B | Output
0 0 |   1    ← only 0+0 gives 1
0 1 |   0
1 0 |   0
1 1 |   0

Note: CMOS always: PMOS pull-up network is dual of NMOS pull-down.

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3. HDL — Hardware Description Language

Verilog Basics

// Module declaration
module adder_4bit (
    input  [3:0] a,      // 4-bit input
    input  [3:0] b,
    input        cin,    // carry in
    output [3:0] sum,
    output       cout    // carry out
);
    assign {cout, sum} = a + b + cin;  // Continuous assignment
endmodule

// Testbench
module tb_adder;
    reg [3:0] a, b;
    reg cin;
    wire [3:0] sum;
    wire cout;

    adder_4bit uut (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

    initial begin
        a = 4'b0101; b = 4'b0011; cin = 0; #10;
        a = 4'b1111; b = 4'b0001; cin = 0; #10;
        $display("Sum = %b, Cout = %b", sum, cout);
        $finish;
    end
endmodule

// D Flip-Flop — sequential logic
module dff (
    input  clk, rst, d,
    output reg q
);
    always @(posedge clk or posedge rst) begin
        if (rst) q <= 1'b0;  // Async reset
        else     q <= d;      // Clock edge capture
    end
endmodule

// 4-bit Counter
module counter (
    input  clk, rst,
    output reg [3:0] count
);
    always @(posedge clk or posedge rst) begin
        if (rst)       count <= 4'b0000;
        else           count <= count + 1;
    end
endmodule

Combinational vs Sequential

| Feature | Combinational | Sequential | |---------|--------------|------------| | Output depends on | Current inputs only | Inputs + past state | | Memory | No | Yes (flip-flops) | | Clock | Not needed | Required | | Examples | Adder, MUX, decoder | Register, counter, FSM |

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4. Logic Synthesis

RTL → Gate-level Netlist:

Verilog RTL Code
    ↓ [Synthesis tool: Synopsys DC, Cadence Genus]
Generic Boolean equations
    ↓ [Technology mapping]
Standard Cell Library gates (AND, OR, FF, Buffer)
    ↓
Gate-level netlist (.v or .sdf)

Standard Cell Library:

• Pre-designed, pre-characterized cells
• Each cell: schematic + layout + timing model
• Typical: INV, BUF, AND2, OR2, NAND2, NOR2, MUX2, DFF

Optimization objectives:

• Area — minimize gate count
• Power — minimize switching activity
• Timing — meet clock frequency (critical path)

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5. Timing Analysis

Critical Path & Setup/Hold

         FF1                      FF2
CLK ─────► Q ──► [Logic] ──► D ─────► Q
              T_clktoQ + T_logic < T_period - T_setup

Setup Time (Tsu): D must be stable before clock edge

T_clk-to-Q + T_logic < T_period - T_setup
→ Max operating frequency = 1 / (T_clk-to-Q + T_logic + T_setup)

Hold Time (Th): D must remain stable after clock edge

T_clk-to-Q + T_logic > T_hold

Slack:

• Positive slack → timing met (margin available)
• Zero slack → timing just met
• Negative slack → timing violation → chip won't work at target freq

Static Timing Analysis (STA):

Tools: Synopsys PrimeTime, Cadence Tempus
Reports: setup/hold slack, critical path, worst negative slack

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6. Physical Design Flow

Netlist + Constraints
    ↓
1. Floorplanning
   - Die area, core area, aspect ratio
   - I/O pad placement
   - Macro placement (RAMs, IPs)

2. Power Planning
   - Power rings, stripes
   - VDD/GND rail distribution

3. Placement
   - Standard cells placed in rows
   - Timing-driven placement

4. Clock Tree Synthesis (CTS)
   - Balanced clock distribution
   - Minimize clock skew

5. Routing
   - Global routing → Detailed routing
   - Metal layers (M1-M9+)

6. Sign-off Checks
   - DRC (Design Rule Check)
   - LVS (Layout vs Schematic)
   - RC Extraction → STA
   - IR Drop Analysis
   - EM (Electromigration) Check

7. GDSII Generation → Tape-out

DRC — Design Rule Check

Physical rules imposed by fabrication process:

• Minimum width of metal wire
• Minimum spacing between wires
• Via size requirements
• Poly-to-diffusion spacing

LVS — Layout vs Schematic

Verify that physical layout matches original schematic:

• Same devices (transistors, resistors)
• Same connections
• Same device sizes

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Exam Important Questions

1. CMOS inverter ka working explain karo with diagram
2. NAND aur NOR gate ka CMOS implementation draw karo
3. VLSI design flow step-by-step explain karo
4. RTL design kya hai? Verilog mein 4-bit counter likhein
5. Setup time aur Hold time kya hain? Violation se kya hota hai?
6. Physical design mein CTS (Clock Tree Synthesis) kyun zaroori hai?
7. DRC aur LVS kya hain? Kyon important hain tape-out se pehle?
8. Moore's law kya hai aur aaj uski limitations kya hain?

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Viva Questions

Q: FinFET kyun introduce hua planar MOSFET ke baad? A: 22nm se neeche planar MOSFET mein severe short-channel effects aur leakage current badh gayi. FinFET 3D structure (fin) se better gate control, lower leakage, aur continued scaling enable karta hai.

Q: Synchronous aur Asynchronous reset mein kya fark hai? A: Synchronous reset sirf clock edge pe activate hota hai (timing-friendly). Asynchronous reset kisi bhi waqt activate ho sakta hai (immediate response, lekin timing analysis complex).

Q: Clock skew kya hai aur kyon problem hai? A: Ek hi clock signal ke alag flip-flops tak pahunchne mein time difference = clock skew. Zyada skew setup/hold violations cause kar sakta hai.