Computer Organization and Architecture — Complete Notes

Unit 1: Basic Computer Organization

A computer consists of five functional units:

Von Neumann Architecture:

• CPU (Central Processing Unit): ALU + Control Unit + Registers
• Memory Unit: Stores programs and data
• Input Unit: Keyboard, mouse, scanner
• Output Unit: Monitor, printer
• Storage: Hard disk, SSD

CPU Components:

• ALU (Arithmetic Logic Unit): Performs arithmetic (+,-,*,/) and logical (AND,OR,NOT) operations
• Control Unit (CU): Fetches, decodes, and executes instructions; controls data flow
• Registers: Small, fastest storage inside CPU
  • PC (Program Counter): address of next instruction
  • IR (Instruction Register): current instruction being executed
  • MAR (Memory Address Register): address for memory access
  • MDR (Memory Data Register): data being transferred to/from memory
  • AC (Accumulator): main working register

Instruction Cycle (Fetch-Decode-Execute):

1. Fetch: PC→MAR, Memory[MAR]→MDR→IR, PC++
2. Decode: Control Unit decodes IR
3. Execute: ALU performs operation
4. Store: Result stored in register or memory

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Unit 2: Instruction Formats and Addressing Modes

Instruction Format

An instruction = Opcode + Operand(s)

| Format | Structure | Example | |---|---|---| | Zero Address | Opcode only (Stack-based) | PUSH, POP | | One Address | Opcode + 1 operand (Accumulator) | LOAD X | | Two Address | Opcode + 2 operands | ADD R1, R2 | | Three Address | Opcode + 3 operands | ADD R1, R2, R3 |

Addressing Modes

How the operand location is specified:

| Mode | Description | Effective Address | |---|---|---| | Immediate | Operand is the value itself | No memory access | | Direct | Address field = memory address | EA = A | | Indirect | Address field = address of address | EA = M[A] | | Register | Operand in register | EA = register | | Register Indirect | Register holds address | EA = M[R] | | Indexed | EA = Index Register + Offset | EA = IR + A | | Base Relative | EA = Base Register + Displacement | EA = BR + A | | Auto-Increment | Use register, then increment | Good for arrays |

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Unit 3: Memory Organization

Memory Hierarchy (Fastest to Slowest, Smallest to Largest)

Registers → Cache (L1/L2/L3) → RAM → SSD/HDD → Cloud Storage

| Level | Speed | Size | Cost/Bit | |---|---|---|---| | Registers | ~1 ns | 32-256 bytes | Very High | | L1 Cache | ~1 ns | 32-64 KB | High | | L2 Cache | ~5 ns | 256 KB - 1 MB | High | | L3 Cache | ~20 ns | 4-32 MB | Moderate | | RAM (DRAM) | ~50-100 ns | 4-64 GB | Low | | SSD | ~0.1 ms | 256 GB - 2 TB | Very Low | | HDD | ~5-10 ms | 1-20 TB | Cheapest |

Cache Memory

Principle of Locality:

• Temporal: Recently accessed data likely accessed again
• Spatial: Data near recently accessed data likely accessed soon

Cache Mapping Techniques:

1. Direct Mapping: Each main memory block maps to exactly one cache line

   • Simple but high conflict misses
   • Index = Block number mod Cache size

2. Fully Associative: Block can go to any cache line

   • Flexible but complex search

3. Set Associative (k-way): Cache divided into sets; block maps to a set

   • Compromise between direct and fully associative
   • Most commonly used

Replacement Policies:

• LRU (Least Recently Used): Replace oldest-used block — best performance
• FIFO: Replace oldest block in cache
• Random: Replace random block — simple

Cache Performance:

Average Access Time = Hit Rate × Cache Time + Miss Rate × Main Memory Time
Miss Rate = 1 - Hit Rate

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Unit 4: Pipelining

Pipelining allows overlapping multiple instruction executions to improve throughput.

Classic 5-Stage Pipeline:

IF (Instruction Fetch) → ID (Decode) → EX (Execute) → MEM (Memory) → WB (Write Back)

Speedup Formula:

Speedup = n / (1 + pipeline stages × stall cycles)
Ideal speedup = k (number of pipeline stages)

Pipeline Hazards:

| Hazard | Cause | Solution | |---|---|---| | Structural | Two instructions need same hardware | Stall or duplicate hardware | | Data (RAW) | Instruction needs result of previous | Forwarding/Bypassing, Stall | | Control (Branch) | Branch direction unknown | Branch prediction, Delayed branch |

Data Hazards (Types):

• RAW (Read After Write): Most common — instruction reads before previous writes
• WAR (Write After Read): Anti-dependency
• WAW (Write After Write): Output dependency

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Unit 5: I/O Organization

I/O Techniques

| Technique | CPU Involvement | Speed | Use | |---|---|---|---| | Programmed I/O | 100% (polling) | Slow | Simple devices | | Interrupt-Driven | Only at completion | Better | Keyboard, mouse | | DMA | Minimal (setup only) | Fast | Disk, Network |

DMA (Direct Memory Access):

• DMA controller handles data transfer between I/O and memory
• CPU only sets up transfer; DMA does the work
• CPU free to do other tasks during transfer
• DMA sends interrupt when done

Buses

• Data Bus: Carries data (bidirectional)
• Address Bus: Carries memory address (unidirectional CPU→memory)
• Control Bus: Carries control signals

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RISC vs CISC

| Feature | RISC | CISC | |---|---|---| | Instruction Set | Small, simple | Large, complex | | Instruction Length | Fixed | Variable | | Addressing Modes | Few | Many | | Execution | 1 clock per instruction | Multiple clocks | | Registers | Many | Few | | Examples | ARM, MIPS, RISC-V | x86, Intel | | Use | Mobile, embedded | Desktop, server |

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Solved PYQ Questions

Q1 (2023): What is the speedup of a 4-stage pipeline executing 100 instructions? Without pipeline: 100 × 4 = 400 cycles With pipeline: 4 + (100-1) × 1 = 103 cycles Speedup = 400/103 ≈ 3.88x

Q2 (2022): Calculate average access time: cache hit rate 90%, cache time 10ns, RAM time 100ns Average = 0.90 × 10 + 0.10 × 100 = 9 + 10 = 19 ns

Q3 (2023): What are the advantages of pipelining? Increases throughput (instructions per second), better CPU utilization, allows parallel instruction execution, reduces effective CPI (Cycles Per Instruction).

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Quick Revision Checklist

• 5 CPU components: ALU, CU, Registers, Cache, Buses
• 4 addressing modes: immediate, direct, indirect, indexed
• Memory hierarchy: registers → cache → RAM → disk
• Cache mapping: direct, fully associative, set associative
• Cache hit rate formula for average access time
• 5-stage pipeline stages: IF, ID, EX, MEM, WB
• 3 pipeline hazards: structural, data, control — and solutions
• DMA: CPU setup only; DMA controller handles transfer
• RISC vs CISC: all differences